From e08ce61fbec9342c2b098ba7d0bd392507978321 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 10 Jul 2019 16:06:07 +0200 Subject: [PATCH] Modified 015 to include DFFMUX.MC31 for SLICEM Signed-off-by: Maciej Kurc --- fuzzers/015-clb-nffmux/Makefile | 10 +++- fuzzers/015-clb-nffmux/generate.py | 17 +++++- fuzzers/015-clb-nffmux/top.py | 96 ++++++++++++++++++++++-------- 3 files changed, 93 insertions(+), 30 deletions(-) diff --git a/fuzzers/015-clb-nffmux/Makefile b/fuzzers/015-clb-nffmux/Makefile index 8ebcd2c2..6980f1f4 100644 --- a/fuzzers/015-clb-nffmux/Makefile +++ b/fuzzers/015-clb-nffmux/Makefile @@ -1,4 +1,8 @@ -N := 3 -CLB_DBFIXUP=Y -include ../clb.mk +# Specimen count +N := 5 + +# A grep regex for SLICEM features to be skipped for SLICELs +SLICEM_FEATURES ?= "DFFMUX.MC31" + +include ../clb_ext.mk diff --git a/fuzzers/015-clb-nffmux/generate.py b/fuzzers/015-clb-nffmux/generate.py index 3fa520ad..45b24ab7 100644 --- a/fuzzers/015-clb-nffmux/generate.py +++ b/fuzzers/015-clb-nffmux/generate.py @@ -59,12 +59,25 @@ for l in f: # create 0-tags for all sources on the remaining (unused) MUXes for loc, muxes in cache.items(): for which in muxes: - for src in "F7 F8 CY O5 AX XOR O6".split(): + for src in "F7 F8 CY O5 AX XOR O6 MC31".split(): + if src == "MC31" and which is not "D": continue if src == "F7" and which not in "AC": continue if src == "F8" and which not in "B": continue if src == "AX": src = which + "X" tag = "%sFFMUX.%s" % (which, src) segmk.add_site_tag(loc, tag, 0) -segmk.compile(bitfilter=util.bitfilter_clb_mux) +def bitfilter(frame_idx, bit_idx): + + # Since the SRL32 is enabled along with DFFMUX.MC31, bits related to + # SRL32 features are masked out. + if (frame_idx, bit_idx) in [ + (30, 16), # ALUT.SRL + ( 1, 23), # WEMUX.CE + ]: + return False + + return util.bitfilter_clb_mux(frame_idx, bit_idx) + +segmk.compile(bitfilter=bitfilter) segmk.write() diff --git a/fuzzers/015-clb-nffmux/top.py b/fuzzers/015-clb-nffmux/top.py index 90769867..f5b5b9be 100644 --- a/fuzzers/015-clb-nffmux/top.py +++ b/fuzzers/015-clb-nffmux/top.py @@ -6,17 +6,18 @@ from prjxray import verilog # INCREMENT is the amount of additional CLBN to be instantiated in the design. # This makes the fuzzer compilation more robust against failures. INCREMENT = os.getenv('CLBN', 0) -CLBN = 400 + int(INCREMENT) +CLBN = 600 + int(INCREMENT) print('//Requested CLBs: %s' % str(CLBN)) - -def gen_slices(): - for _tile_name, site_name, _site_type in util.get_roi().gen_sites([ - 'SLICEL', - 'SLICEM', - ]): +def gen_slicels(): + for _tile_name, site_name, _site_type in util.get_roi().gen_sites( + ['SLICEL']): yield site_name +def gen_slicems(): + for _tile_name, site_name, _site_type in util.get_roi().gen_sites( + ['SLICEM']): + yield site_name DIN_N = CLBN * 8 DOUT_N = CLBN * 8 @@ -25,22 +26,31 @@ verilog.top_harness(DIN_N, DOUT_N) f = open('params.csv', 'w') f.write('module,loc,n\n') -slices = gen_slices() +slicels = gen_slicels() +slicems = gen_slicems() print( 'module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1)) for i in range(CLBN): - modules = [ - 'clb_NFFMUX_' + x for x in ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR'] - ] + + use_slicem = (i % 2) == 0 + + if use_slicem: + loc = next(slicems) + variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR', 'MC31'] + else: + loc = next(slicels) + variants = ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR'] + + modules = ['clb_NFFMUX_' + x for x in variants] module = random.choice(modules) - if module == 'clb_NFFMUX_F78': + if module == 'clb_NFFMUX_MC31': + n = 3 # Only DOUTMUX has MC31 input + elif module == 'clb_NFFMUX_F78': n = random.randint(0, 2) else: n = random.randint(0, 3) - #n = 0 - loc = next(slices) print(' %s' % module) print(' #(.LOC("%s"), .N(%d))' % (loc, n)) @@ -65,10 +75,12 @@ module myLUT8 (input clk, input [7:0] din, //carco: CLA result (carry module additional output) output caro, output carco, output bo5, output bo6, + output wire mc31, output wire ff_q, //always connect to output input wire ff_d); //mux output net parameter LOC="SLICE_FIXME"; parameter N=-1; + parameter ALUT_SRL=0; wire [3:0] caro_all; assign caro = caro_all[N]; @@ -127,18 +139,37 @@ module myLUT8 (input clk, input [7:0] din, .O5(lutno5[1]), .O6(lutno6[1])); + generate if (ALUT_SRL != 0) begin + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) - LUT6_2 #( - .INIT(64'h8000_1CE0_0000_0001) - ) luta ( - .I0(din[0]), - .I1(din[1]), - .I2(din[2]), - .I3(din[3]), - .I4(din[4]), - .I5(din[5]), - .O5(lutno5[0]), - .O6(lutno6[0])); + SRLC32E #( + .INIT(64'h8000_1CE0_0000_0001) + ) srla ( + .CLK(clk), + .CE(din[6]), + .D(din[5]), + .A(din[4:0]), + .Q(lutno6[0]), + .Q31(mc31)); + + assign lutno5[0] = din[6]; + + end else begin + + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) + LUT6_2 #( + .INIT(64'h8000_1CE0_0000_0001) + ) luta ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(lutno5[0]), + .O6(lutno6[0])); + + end endgenerate //Outputs do not have to be used, will stay without them (* LOC=LOC, KEEP, DONT_TOUCH *) @@ -302,4 +333,19 @@ module clb_NFFMUX_XOR (input clk, input [7:0] din, output [7:0] dout); .ff_q(dout[0]), .ff_d(caro)); endmodule + +module clb_NFFMUX_MC31 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + parameter N=-1; // Dummy + wire mc31; + + myLUT8 #(.LOC(LOC), .N(3), .ALUT_SRL(1)) + myLUT8(.clk(clk), .din(din), + .lut8o(), + .caro(caro), .carco(), + .bo5(), .bo6(bo6), + .mc31(mc31), + .ff_q(dout[0]), + .ff_d(mc31)); +endmodule ''')