From dd5305a2717ae82423345818ba4e0f0e3baaf936 Mon Sep 17 00:00:00 2001
From: Rick Altherr <raltherr@google.com>
Date: Mon, 5 Feb 2018 16:08:20 -0800
Subject: [PATCH] docs: Define some terms

Tried to merge definitions from wiki/Glossary and my understandings of
terms related to architecture and configuration.

Signed-off-by: Rick Altherr <raltherr@google.com>
---
 docs/architecture/glossary.rst | 67 ++++++++++++++++++++++++++++++++++
 docs/index.rst                 |  1 +
 2 files changed, 68 insertions(+)
 create mode 100644 docs/architecture/glossary.rst

diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst
new file mode 100644
index 00000000..ab798595
--- /dev/null
+++ b/docs/architecture/glossary.rst
@@ -0,0 +1,67 @@
+Glossary
+========================
+
+.. glossary::
+
+  basic element
+  BEL
+  basic logic element
+  BLE
+    For example a LUT5, LUT6, CARRY4, or MUX, but not PIPs.
+
+    BELs come in two types:
+
+    * Basic BEL - A logic unit which does things.
+    * Routing BEL - A unit which is statically configured at the routing time.
+     
+
+  bitstream
+    Binary data that is directly loaded into an FPGA to perform configuration.
+    Contains configuration :term:`frames <frame>` as well as programming
+    sequences and other commands required to load and activate same.
+
+  column
+    Collection of :term:`tiles <tile>` physically organized as a vertical line.
+
+  configurable logic block
+  CLB
+    Basic building block of logic. 
+
+  frame
+    Fundamental unit of configuration data consisting of 101 :term:`words <word>`.
+
+  half
+    Portion of a device defined by a virtual line dividing the two sets of global
+    clock buffers present in a device. The two halves are simply referred to as
+    the top and bottom halves.
+
+  node
+    Collection of :term:`wires <wire>` spanning one or more tiles.
+
+  programmable interconnect point
+  PIP
+    Connection point between two wires in a tile that may be enabled or
+    disabled by the configuration.
+
+  horizontal clock row
+    Portion of a device including 12 horizontal clocks and the 50 interconnect
+    and function tiles associated with them. A :term:`half` contains one or
+    more horizontal clock rows and each half may have a different number of
+    rows.
+
+  site
+    Portion of a tile where :term:`BELs <BEL>` can be placed.  :term:`Slices
+    <slice>` in a :term:`CLB` tile are sites.
+
+  slice
+    Portion of a :term:`CLB` tile that contains :term:`BELs <BEL>`.
+
+  tile
+    Fundamental unit of physical structure containing a single type of
+    resource or function.
+
+  wire
+    Physical wire within a :term:`tile`.
+
+  word
+    32-bits stored in big-endian order. Fundamental unit of :term:`bitstream` format. 
diff --git a/docs/index.rst b/docs/index.rst
index 0f4b2898..51041785 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -17,3 +17,4 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    :maxdepth: 2
    :caption: Xilinx 7-series Architecture
 
+   architecture/glossary