From da6829f857ef4eb3b087e754ba51389700ea2950 Mon Sep 17 00:00:00 2001 From: regymm <31496626+regymm@users.noreply.github.com> Date: Fri, 27 Dec 2024 16:52:49 +0900 Subject: [PATCH] Added Zynq 7030, 7035, 7045, 7100 support --- .gitignore | 1 + Makefile | 2 +- fuzzers/005-tilegrid/Makefile | 78 ++++---- fuzzers/005-tilegrid/iob/top.py | 8 + fuzzers/005-tilegrid/iob_int/top.py | 11 ++ fuzzers/005-tilegrid/util.py | 9 +- fuzzers/035-iob-ilogic/Makefile | 2 +- fuzzers/035b-iob-iserdes/Makefile | 2 +- fuzzers/039-hclk-config/Makefile | 9 +- .../zynq7/xc7z030fbg676-1_ignored_wires.txt | 110 +++++++++++ .../zynq7/xc7z045ffg900-1_ignored_wires.txt | 176 ++++++++++++++++++ .../zynq7/xc7z100ffg1156-1_ignored_wires.txt | 176 ++++++++++++++++++ fuzzers/075-pins/Makefile | 4 + fuzzers/Makefile | 23 ++- settings/zynq7/devices.yaml | 8 + settings/zynq7030.sh | 41 ++++ settings/zynq7045.sh | 49 +++++ settings/zynq7100.sh | 41 ++++ 18 files changed, 707 insertions(+), 43 deletions(-) create mode 100644 fuzzers/074-dump_all/ignored_wires/zynq7/xc7z030fbg676-1_ignored_wires.txt create mode 100644 fuzzers/074-dump_all/ignored_wires/zynq7/xc7z045ffg900-1_ignored_wires.txt create mode 100644 fuzzers/074-dump_all/ignored_wires/zynq7/xc7z100ffg1156-1_ignored_wires.txt create mode 100644 settings/zynq7030.sh create mode 100644 settings/zynq7045.sh create mode 100644 settings/zynq7100.sh diff --git a/.gitignore b/.gitignore index b4257487..19bae9ec 100644 --- a/.gitignore +++ b/.gitignore @@ -9,6 +9,7 @@ settings/*/resources.yaml **/output run.ok run.*.ok +run-*.*.ok __pycache__ *.pyc *.swp diff --git a/Makefile b/Makefile index e4624384..8b74722c 100644 --- a/Makefile +++ b/Makefile @@ -188,7 +188,7 @@ $(foreach DB,$(DATABASES),$(eval $(call database,$(DB)))) # -------------------------------------- ARTIX_PARTS=artix7_50t artix7_200t -ZYNQ_PARTS=zynq7010 +ZYNQ_PARTS=zynq7010 zynq7030 zynq7045 zynq7100 KINTEX_PARTS=kintex7_160t kintex7_325t kintex7_420t kintex7_480t SPARTAN_PARTS= diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index 57716950..c4ad8de9 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -45,6 +45,16 @@ endif # Zynq7 only fuzzers ifeq (${XRAY_DATABASE}, zynq7) TILEGRID_TDB_DEPENDENCIES += ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb +ifeq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7z030 xc7z045 xc7z100)) +TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb +TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb +TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb +#TILEGRID_TDB_DEPENDENCIES += pcie/$(BUILD_FOLDER)/segbits_tilegrid.tdb +#TILEGRID_TDB_DEPENDENCIES += pcie_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb +# TODO: This has issue with 7030: tdb uncertainty? +#PCIE_INT_INTERFACE_L_X66Y0.DWORD:0.AUTO_FRAME 0044211A_000_00 +#PCIE_INT_INTERFACE_R_X63Y0.DWORD:0.AUTO_FRAME <6 candidates> +endif endif # Kintex7 only fuzzers @@ -80,98 +90,100 @@ ${BASICDB_TILEGRID}: generate.py $(BUILD_FOLDER)/tiles/tiles.txt --pin_func $(BUILD_DIR)/tiles/pin_func.txt \ --out ${BUILD_DIR}/basicdb/${XRAY_FABRIC}/tilegrid.json +OKFLAG=run-005.${XRAY_PART}.ok + clb/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd clb && $(MAKE) + cd clb && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) clb_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd clb_int && $(MAKE) + cd clb_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) cfg/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd cfg && $(MAKE) + cd cfg && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd iob && $(MAKE) + cd iob && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd iob18 && $(MAKE) + cd iob18 && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd iob_int && $(MAKE) + cd iob_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd iob18_int && $(MAKE) + cd iob18_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd ioi && $(MAKE) + cd ioi && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd ioi18 && $(MAKE) + cd ioi18 && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) mmcm/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd mmcm && $(MAKE) + cd mmcm && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) pll/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd pll && $(MAKE) + cd pll && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd ps7_int && $(MAKE) + cd ps7_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd monitor && $(MAKE) + cd monitor && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) monitor_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd monitor_int && $(MAKE) + cd monitor_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd bram && $(MAKE) + cd bram && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd bram_block && $(MAKE) + cd bram_block && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) bram_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd bram_int && $(MAKE) + cd bram_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) dsp/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd dsp && $(MAKE) + cd dsp && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) dsp_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd dsp_int && $(MAKE) + cd dsp_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) fifo_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd fifo_int && $(MAKE) + cd fifo_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) cfg_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd cfg_int && $(MAKE) + cd cfg_int && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd orphan_int_column && $(MAKE) + cd orphan_int_column && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) clk_hrow/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd clk_hrow && $(MAKE) + cd clk_hrow && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) clk_bufg/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd clk_bufg && $(MAKE) + cd clk_bufg && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) hclk_cmt/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd hclk_cmt && $(MAKE) + cd hclk_cmt && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) hclk_ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd hclk_ioi && $(MAKE) + cd hclk_ioi && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) pcie/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd pcie && $(MAKE) + cd pcie && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) pcie_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd pcie_int_interface && $(MAKE) + cd pcie_int_interface && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) gtp_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd gtp_common && $(MAKE) + cd gtp_common && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) gtp_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd gtp_channel && $(MAKE) + cd gtp_channel && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) gtp_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID} - cd gtp_int_interface && $(MAKE) + cd gtp_int_interface && test -s ${OKFLAG} || ($(MAKE) && touch ${OKFLAG}) $(BUILD_FOLDER)/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES) python3 add_tdb.py \ @@ -189,7 +201,8 @@ run: clean: rm -rf build_* run.*.ok - cd clb && $(MAKE) clean + find . | grep run-005.*.ok | xargs rm -rf + cd clb && rm run.${XRAY_PART}.ok && $(MAKE) clean cd clb_int && $(MAKE) clean cd cfg && $(MAKE) clean cd iob && $(MAKE) clean @@ -222,6 +235,7 @@ clean: cd gtp_int_interface && $(MAKE) clean clean_part: + find . | grep ${OKFLAG} | xargs rm -rf rm -rf $(BUILD_FOLDER) run.${XRAY_PART}.ok cd clb && $(MAKE) clean_part cd clb_int && $(MAKE) clean_part diff --git a/fuzzers/005-tilegrid/iob/top.py b/fuzzers/005-tilegrid/iob/top.py index 8734755e..dd0f57c0 100644 --- a/fuzzers/005-tilegrid/iob/top.py +++ b/fuzzers/005-tilegrid/iob/top.py @@ -30,6 +30,14 @@ def gen_sites(): for site_name, site_type in gridinfo.sites.items(): if site_type == 'IOB33S': + # Zynq 7045 have an nearly unbonded IO bank X0Y0 even on largest footprint + is_7045 = "xc7z045" in os.environ["XRAY_PART"] + unbonded_ios = ["LIOB33_X0Y" + str(i) for i in + [1, 3, 5, 7, 9, 13, 15, 17, 19, 29, 31, 33, 35, 39, 41, 43, 45, 47]] + unbonded_ios.append("LIOI3_SING_X0Y0") + unbonded_ios.append("LIOI3_SING_X0Y49") + if (is_7045 and tile_name in unbonded_ios): + continue yield tile_name, site_name diff --git a/fuzzers/005-tilegrid/iob_int/top.py b/fuzzers/005-tilegrid/iob_int/top.py index e1d6f8da..5a03c048 100644 --- a/fuzzers/005-tilegrid/iob_int/top.py +++ b/fuzzers/005-tilegrid/iob_int/top.py @@ -30,7 +30,18 @@ def gen_sites(): ''' db = Database(util.get_db_root(), util.get_part()) grid = db.grid() + + is_7045 = "xc7z045" in os.environ["XRAY_PART"] + unbonded_iois = [] + for i in [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47]: + unbonded_iois.append("LIOI3_X0Y" + str(i)) + unbonded_iois.append("LIOI3_TBYTESRC_X0Y" + str(i)) + unbonded_iois.append("LIOI3_TBYTETERM_X0Y" + str(i)) + unbonded_iois.append("LIOI3_SING_X0Y0") + unbonded_iois.append("LIOI3_SING_X0Y49") for tile_name in sorted(grid.tiles()): + if is_7045 and tile_name in unbonded_iois: + continue loc = grid.loc_of_tilename(tile_name) gridinfo = grid.gridinfo_at_loc(loc) diff --git a/fuzzers/005-tilegrid/util.py b/fuzzers/005-tilegrid/util.py index a26e8259..d35b405f 100644 --- a/fuzzers/005-tilegrid/util.py +++ b/fuzzers/005-tilegrid/util.py @@ -119,7 +119,14 @@ def add_tile_bits( done = True verbose and print( "%s: existing defintion for %s" % (tile_name, block_type)) - assert block["baseaddr"] == baseaddr_str + is_7045 = "xc7z045" in os.environ["XRAY_PART"] + if is_7045: + # Has INT_L_X18Y150, orig baseaddr 0x00440900, new 0x00000900 on Zynq 7045 + if block["baseaddr"] != baseaddr_str: + print("orig baseaddr %s, new %s on Zynq 7045" % ( + block["baseaddr"], baseaddr_str)) + else: + assert block["baseaddr"] == baseaddr_str assert block["frames"] == frames, (block, frames) # TODO: HACK: some of the offsets of the K480T seem to be messed up # using the maximum offset below seems to make most sense when looking diff --git a/fuzzers/035-iob-ilogic/Makefile b/fuzzers/035-iob-ilogic/Makefile index 8ac93805..1459e7b8 100644 --- a/fuzzers/035-iob-ilogic/Makefile +++ b/fuzzers/035-iob-ilogic/Makefile @@ -39,7 +39,7 @@ pushdb: build/segbits_rioi.db ${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db ${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db ${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db -ifeq ($(XRAY_DATABASE),kintex7) +ifeq ($(XRAY_DATABASE), $(filter ${XRAY_DATABASE}, kintex7 zynq7)) ${XRAY_MERGEDB} rioi build/segbits_rioi.db ${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db ${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index a8033051..37355750 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -40,7 +40,7 @@ pushdb: build/segbits_rioi.db ${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db ${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db ${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db -ifeq ($(XRAY_DATABASE),kintex7) +ifeq ($(XRAY_DATABASE), $(filter ${XRAY_DATABASE}, kintex7 zynq7)) ${XRAY_MERGEDB} rioi build/segbits_rioi.db ${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db ${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db diff --git a/fuzzers/039-hclk-config/Makefile b/fuzzers/039-hclk-config/Makefile index 4828018f..4e7fcf59 100644 --- a/fuzzers/039-hclk-config/Makefile +++ b/fuzzers/039-hclk-config/Makefile @@ -9,11 +9,10 @@ N ?= 50 include ../fuzzer.mk -ifeq ($(XRAY_DATABASE),kintex7) +ifeq ($(XRAY_DATABASE), $(filter {XRAY_DATABASE}, kintex7 zynq7)) database: build/segbits_hclk_ioi.db -else -database: build/segbits_hclk_ioi3.db endif +database: build/segbits_hclk_ioi3.db build/segbits_hclk_ioi3.rdb: $(SPECIMENS_OK) ${XRAY_SEGMATCH} -c 5 -o build/segbits_hclk_ioi3.rdb \ @@ -28,7 +27,7 @@ build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb # The fuzzer results for the high performance banks # are identical, so just copy those -ifeq ($(XRAY_DATABASE),kintex7) +ifeq ($(XRAY_DATABASE), $(filter {XRAY_DATABASE}, kintex7 zynq7)) build/segbits_hclk_ioi.db: build/segbits_hclk_ioi3.db sed -e 's/HCLK_IOI3/HCLK_IOI/g' $< > $@ cp build/mask_hclk_ioi3.db build/mask_hclk_ioi.db @@ -37,7 +36,7 @@ endif pushdb: database ${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db ${XRAY_MERGEDB} mask_hclk_ioi3 build/mask_hclk_ioi3.db -ifeq ($(XRAY_DATABASE),kintex7) +ifeq ($(XRAY_DATABASE), $(filter {XRAY_DATABASE}, kintex7 zynq7)) ${XRAY_MERGEDB} hclk_ioi build/segbits_hclk_ioi.db ${XRAY_MERGEDB} mask_hclk_ioi build/mask_hclk_ioi.db endif diff --git a/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z030fbg676-1_ignored_wires.txt b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z030fbg676-1_ignored_wires.txt new file mode 100644 index 00000000..dfde353b --- /dev/null +++ b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z030fbg676-1_ignored_wires.txt @@ -0,0 +1,110 @@ +RIOI_TBYTESRC_X79Y169/RIOI_I2GCLK_BOT1 +LIOI3_X0Y55/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_BOT1 +LIOI3_X0Y95/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y143/RIOI_I2GCLK_BOT1 +RIOI_X79Y129/RIOI_I2GCLK_TOP1 +RIOI_X79Y159/RIOI_I2GCLK_BOT1 +LIOI3_X0Y59/LIOI_I2GCLK_BOT1 +LIOI3_X0Y9/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y107/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y119/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y57/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y163/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y69/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y157/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X195Y135/CMT_PHASER_UP_DQS_TO_PHASER_D +CMT_TOP_R_LOWER_T_X8Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTETERM_X79Y137/RIOI_I2GCLK_TOP1 +LIOI3_X0Y71/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y63/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y169/RIOI_I2GCLK_TOP1 +RIOI_X79Y55/RIOI_I2GCLK_TOP1 +RIOI_X79Y91/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_BOT1 +LIOI3_X0Y91/LIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X195Y187/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTESRC_X79Y143/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y131/RIOI_I2GCLK_TOP1 +RIOI_X79Y79/RIOI_I2GCLK_TOP1 +LIOI3_X0Y67/LIOI_I2GCLK_TOP1 +RIOI_X79Y167/RIOI_I2GCLK_TOP1 +RIOI_X79Y133/RIOI_I2GCLK_BOT1 +RIOI_X79Y109/RIOI_I2GCLK_BOT1 +LIOI3_X0Y29/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y81/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y119/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y93/RIOI_I2GCLK_BOT1 +RIOI_X79Y171/RIOI_I2GCLK_BOT1 +RIOI_X79Y121/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y181/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y181/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X79Y87/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y57/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y69/RIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y31/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y187/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_TOP1 +LIOI3_X0Y45/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y137/RIOI_I2GCLK_BOT1 +LIOI3_X0Y83/LIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X195Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X79Y131/RIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X195Y122/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_TOP1 +RIOI_X79Y195/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y163/RIOI_I2GCLK_BOT1 +RIOI_X79Y183/RIOI_I2GCLK_BOT1 +RIOI_X79Y83/RIOI_I2GCLK_BOT1 +RIOI_X79Y145/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y193/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X79Y107/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_TOP1 +LIOI3_X0Y41/LIOI_I2GCLK_TOP1 +LIOI3_X0Y17/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y93/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X79Y113/RIOI_I2GCLK_BOT1 +RIOI_X79Y71/RIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X195Y174/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_TOP1 +LIOI3_X0Y21/LIOI_I2GCLK_BOT1 +RIOI_X79Y141/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y81/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y63/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_BOT1 +RIOI_X79Y105/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_TOP1 +RIOI_X79Y155/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y193/RIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X195Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTETERM_X79Y187/RIOI_I2GCLK_TOP1 +RIOI_X79Y191/RIOI_I2GCLK_TOP1 +RIOI_X79Y179/RIOI_I2GCLK_TOP1 +RIOI_X79Y117/RIOI_I2GCLK_TOP1 +LIOI3_X0Y5/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X79Y113/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_TOP1 +RIOI_X79Y67/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X79Y157/RIOI_I2GCLK_TOP1 +LIOI3_X0Y79/LIOI_I2GCLK_TOP1 +RIOI_X79Y59/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1 +RIOI_X79Y95/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X79Y87/RIOI_I2GCLK_TOP1 +LIOI3_X0Y33/LIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A diff --git a/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z045ffg900-1_ignored_wires.txt b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z045ffg900-1_ignored_wires.txt new file mode 100644 index 00000000..49d72c31 --- /dev/null +++ b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z045ffg900-1_ignored_wires.txt @@ -0,0 +1,176 @@ +RIOI_X107Y267/RIOI_I2GCLK_TOP1 +RIOI_X107Y329/RIOI_I2GCLK_TOP1 +LIOI3_X0Y79/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y187/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTETERM_X107Y213/RIOI_I2GCLK_BOT1 +RIOI_X107Y255/RIOI_I2GCLK_TOP1 +CMT_TOP_L_LOWER_T_X258Y278/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTETERM_X107Y263/RIOI_I2GCLK_TOP1 +RIOI_X107Y221/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_TOP1 +LIOI3_X0Y205/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y313/RIOI_I2GCLK_TOP1 +RIOI_X107Y321/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y237/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X258Y239/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y237/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_TOP1 +RIOI_X107Y217/RIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X258Y343/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_TOP1 +LIOI3_X0Y191/LIOI_I2GCLK_TOP1 +LIOI3_X0Y229/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_TOP1 +CMT_TOP_L_LOWER_T_X258Y330/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y17/LIOI_I2GCLK_TOP1 +LIOI3_X0Y91/LIOI_I2GCLK_TOP1 +LIOI3_X0Y105/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_TOP1 +LIOI3_X0Y233/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y219/LIOI_I2GCLK_TOP1 +LIOI3_X0Y21/LIOI_I2GCLK_BOT1 +LIOI3_X0Y159/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y226/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y71/LIOI_I2GCLK_BOT1 +LIOI3_X0Y217/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y237/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y219/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y343/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_BOT1 +RIOI_X107Y205/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X107Y263/RIOI_I2GCLK_BOT1 +RIOI_X107Y241/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y174/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y337/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_BOT1 +LIOI3_X0Y209/LIOI_I2GCLK_BOT1 +LIOI3_X0Y29/LIOI_I2GCLK_TOP1 +RIOI_X107Y245/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y219/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_BOT1 +LIOI3_X0Y245/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X107Y337/RIOI_I2GCLK_BOT1 +CMT_TOP_L_UPPER_B_X258Y291/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTESRC_X107Y331/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y281/RIOI_I2GCLK_TOP1 +RIOI_X107Y279/RIOI_I2GCLK_TOP1 +LIOI3_X0Y129/LIOI_I2GCLK_TOP1 +LIOI3_X0Y67/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y231/LIOI_I2GCLK_TOP1 +LIOI3_X0Y45/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X107Y287/RIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y83/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y237/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y281/RIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y135/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_X107Y283/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y343/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y207/RIOI_I2GCLK_BOT1 +LIOI3_X0Y41/LIOI_I2GCLK_TOP1 +LIOI3_X0Y183/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_TOP1 +RIOI_X107Y209/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y31/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_X0Y195/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_BOT1 +RIOI_X107Y309/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y293/RIOI_I2GCLK_TOP1 +LIOI3_X0Y117/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_BOT1 +RIOI_X107Y259/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y231/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y213/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y319/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y307/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y243/LIOI_I2GCLK_TOP1 +RIOI_X107Y229/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y213/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y331/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y243/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X107Y313/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y269/RIOI_I2GCLK_BOT1 +RIOI_X107Y317/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y243/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_X107Y271/RIOI_I2GCLK_BOT1 +LIOI3_X0Y167/LIOI_I2GCLK_TOP1 +RIOI_X107Y305/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_BOT1 +LIOI3_X0Y171/LIOI_I2GCLK_BOT1 +LIOI3_X0Y121/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y207/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y257/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y293/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y243/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y231/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y213/LIOI_I2GCLK_TOP1 +LIOI3_X0Y55/LIOI_I2GCLK_TOP1 +LIOI3_X0Y179/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X107Y287/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_TOP1 +LIOI3_X0Y109/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y257/RIOI_I2GCLK_TOP1 +LIOI3_X0Y33/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_BOT1 +RIOI_X107Y291/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y207/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y231/RIOI_I2GCLK_BOT1 +LIOI3_X0Y155/LIOI_I2GCLK_TOP1 +RIOI_X107Y341/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_TOP1 +RIOI_X107Y233/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_TOP1 +RIOI_X107Y333/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_BOT1 +RIOI_X107Y295/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X258Y226/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y5/LIOI_I2GCLK_TOP1 +LIOI3_X0Y141/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y307/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_TOP1 +LIOI3_X0Y221/LIOI_I2GCLK_BOT1 +RIOI_X107Y345/RIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y239/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_X0Y59/LIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y122/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTESRC_X0Y207/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_TOP1 +LIOI3_X0Y133/LIOI_I2GCLK_BOT1 +LIOI3_X0Y145/LIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTESRC_X107Y319/RIOI_I2GCLK_TOP1 +LIOI3_X0Y241/LIOI_I2GCLK_TOP1 +LIOI3_X0Y95/LIOI_I2GCLK_BOT1 +LIOI3_X0Y9/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X107Y269/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X107Y219/RIOI_I2GCLK_BOT1 diff --git a/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z100ffg1156-1_ignored_wires.txt b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z100ffg1156-1_ignored_wires.txt new file mode 100644 index 00000000..b6a86485 --- /dev/null +++ b/fuzzers/074-dump_all/ignored_wires/zynq7/xc7z100ffg1156-1_ignored_wires.txt @@ -0,0 +1,176 @@ +LIOI3_X0Y21/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y307/RIOI_I2GCLK_BOT1 +LIOI3_X0Y209/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y331/RIOI_I2GCLK_BOT1 +LIOI3_X0Y29/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y213/RIOI_I2GCLK_BOT1 +LIOI3_X0Y79/LIOI_I2GCLK_TOP1 +RIOI_X139Y305/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y319/RIOI_I2GCLK_TOP1 +RIOI_X139Y291/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y237/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y257/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_BOT1 +LIOI3_X0Y133/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y83/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTESRC_X139Y281/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y237/LIOI_I2GCLK_TOP1 +LIOI3_X0Y95/LIOI_I2GCLK_BOT1 +RIOI_X139Y295/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y219/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_BOT1 +RIOI_X139Y321/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y237/RIOI_I2GCLK_TOP1 +LIOI3_X0Y9/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y293/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y243/LIOI_I2GCLK_BOT1 +RIOI_X139Y333/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y343/RIOI_I2GCLK_TOP1 +RIOI_X139Y271/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_BOT1 +RIOI_X139Y217/RIOI_I2GCLK_TOP1 +RIOI_X139Y309/RIOI_I2GCLK_BOT1 +LIOI3_X0Y83/LIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X344Y330/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_X139Y341/RIOI_I2GCLK_TOP1 +LIOI3_X0Y105/LIOI_I2GCLK_TOP1 +RIOI_X139Y267/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y219/RIOI_I2GCLK_TOP1 +CMT_TOP_L_UPPER_B_X344Y343/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_TOP1 +LIOI3_X0Y45/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_BOT1 +LIOI3_X0Y191/LIOI_I2GCLK_TOP1 +RIOI_X139Y329/RIOI_I2GCLK_TOP1 +RIOI_X139Y221/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_TOP1 +LIOI3_X0Y71/LIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X139Y343/RIOI_I2GCLK_BOT1 +LIOI3_X0Y159/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y281/RIOI_I2GCLK_BOT1 +LIOI3_X0Y245/LIOI_I2GCLK_BOT1 +LIOI3_X0Y171/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y243/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X139Y313/RIOI_I2GCLK_BOT1 +RIOI_X139Y205/RIOI_I2GCLK_TOP1 +LIOI3_X0Y121/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y213/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_TOP1 +LIOI3_X0Y233/LIOI_I2GCLK_BOT1 +LIOI3_X0Y67/LIOI_I2GCLK_TOP1 +LIOI3_X0Y109/LIOI_I2GCLK_BOT1 +LIOI3_X0Y179/LIOI_I2GCLK_TOP1 +LIOI3_X0Y205/LIOI_I2GCLK_TOP1 +RIOI_X139Y283/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y293/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y243/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y337/RIOI_I2GCLK_TOP1 +LIOI3_X0Y241/LIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y239/CMT_PHASER_UP_DQS_TO_PHASER_D +CMT_TOP_L_UPPER_B_X344Y239/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_X0Y155/LIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y174/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_X0Y55/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y207/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y269/RIOI_I2GCLK_TOP1 +LIOI3_X0Y59/LIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y187/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_TOP1 +LIOI3_X0Y195/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_BOT1 +RIOI_X139Y209/RIOI_I2GCLK_BOT1 +CMT_TOP_R_UPPER_B_X8Y31/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTESRC_X139Y207/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y243/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y231/LIOI_I2GCLK_TOP1 +RIOI_X139Y259/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_BOT1 +CMT_TOP_L_UPPER_B_X344Y291/CMT_PHASER_UP_DQS_TO_PHASER_D +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_TOP1 +LIOI3_X0Y229/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_BOT1 +RIOI_X139Y345/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_BOT1 +RIOI_X139Y245/RIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y269/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y213/LIOI_I2GCLK_BOT1 +LIOI3_X0Y183/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y207/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X139Y263/RIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y213/RIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_BOT1 +LIOI3_X0Y129/LIOI_I2GCLK_TOP1 +RIOI_X139Y279/RIOI_I2GCLK_TOP1 +CMT_TOP_R_UPPER_B_X8Y135/CMT_PHASER_UP_DQS_TO_PHASER_D +RIOI_TBYTETERM_X139Y337/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_TOP1 +CMT_TOP_L_LOWER_T_X344Y226/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y287/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_BOT1 +RIOI_X139Y255/RIOI_I2GCLK_TOP1 +LIOI3_X0Y91/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y319/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y231/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X139Y237/RIOI_I2GCLK_BOT1 +RIOI_X139Y229/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y307/RIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y226/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_X139Y233/RIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X139Y263/RIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y219/LIOI_I2GCLK_BOT1 +RIOI_TBYTESRC_X139Y331/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y231/RIOI_I2GCLK_TOP1 +LIOI3_X0Y17/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_TOP1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_BOT1 +LIOI3_X0Y167/LIOI_I2GCLK_TOP1 +RIOI_X139Y241/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_BOT1 +LIOI3_X0Y141/LIOI_I2GCLK_TOP1 +LIOI3_X0Y217/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_BOT1 +LIOI3_X0Y33/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_BOT1 +LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_BOT1 +LIOI3_X0Y145/LIOI_I2GCLK_BOT1 +CMT_TOP_R_LOWER_T_X8Y122/CMT_PHASER_DOWN_DQS_TO_PHASER_A +LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_BOT1 +LIOI3_X0Y41/LIOI_I2GCLK_TOP1 +LIOI3_X0Y221/LIOI_I2GCLK_BOT1 +RIOI_TBYTETERM_X139Y313/RIOI_I2GCLK_TOP1 +CMT_TOP_R_LOWER_T_X8Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A +RIOI_TBYTESRC_X139Y207/RIOI_I2GCLK_TOP1 +RIOI_TBYTESRC_X139Y257/RIOI_I2GCLK_BOT1 +LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_TOP1 +LIOI3_X0Y5/LIOI_I2GCLK_TOP1 +RIOI_X139Y317/RIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y219/LIOI_I2GCLK_TOP1 +LIOI3_TBYTESRC_X0Y231/LIOI_I2GCLK_BOT1 +LIOI3_X0Y117/LIOI_I2GCLK_TOP1 +RIOI_TBYTETERM_X139Y287/RIOI_I2GCLK_BOT1 +CMT_TOP_L_LOWER_T_X344Y278/CMT_PHASER_DOWN_DQS_TO_PHASER_A diff --git a/fuzzers/075-pins/Makefile b/fuzzers/075-pins/Makefile index 1b167c3e..90d8be21 100644 --- a/fuzzers/075-pins/Makefile +++ b/fuzzers/075-pins/Makefile @@ -16,7 +16,11 @@ database: $(SPECIMENS_OK) pushdb: mkdir -p ${XRAY_FAMILY_DIR}/${XRAY_PART}/ +ifneq ($(filter xc7z045%, ${XRAY_PART}),) + sed '/IOB_X0Y[0-4][0-9]/d' $(BUILD_DIR)/specimen_001/*_package_pins.csv > ${XRAY_FAMILY_DIR}/${XRAY_PART}/package_pins.csv +else cp $(BUILD_DIR)/specimen_001/*_package_pins.csv ${XRAY_FAMILY_DIR}/${XRAY_PART}/package_pins.csv +endif $(SPECIMENS_OK): bash generate.sh $(subst /OK,,$@) diff --git a/fuzzers/Makefile b/fuzzers/Makefile index 9874db60..adde3163 100644 --- a/fuzzers/Makefile +++ b/fuzzers/Makefile @@ -84,10 +84,25 @@ fuzzer_$(1): fuzzer_ok/fuzzer_$(1)_$(XRAY_PART).ok endef +SKIP_DSP=0 +HAS_PCIE=0 +HAS_GTP=0 +HAS_HIGH_PERFORMANCE_BANKS=0 ifeq ($(XRAY_DATABASE),kintex7) HAS_HIGH_PERFORMANCE_BANKS=1 else -HAS_HIGH_PERFORMANCE_BANKS=0 +ifeq ($(XRAY_DATABASE),artix7) +HAS_PCIE=1 +HAS_GTP=1 +else +ifeq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7z030 xc7z045 xc7z100)) +HAS_HIGH_PERFORMANCE_BANKS=1 +# DSP fuzzer gives error on 7030, need to make sure 7020/7010 runs before 7030, and use their results +SKIP_DSP=1 +# PCIE hard block: can only use after GTX support comes +HAS_PCIE=0 +endif +endif endif $(eval $(call fuzzer,000-init-db,,part)) @@ -182,9 +197,11 @@ $(eval $(call fuzzer,075-pins,,part)) ifeq ($(XRAY_DATABASE),zynq7) $(eval $(call fuzzer,076-ps7,,all)) endif -ifeq ($(XRAY_DATABASE),artix7) +ifeq ($(HAS_PCIE),1) $(eval $(call fuzzer,061-pcie-conf,005-tilegrid,all)) $(eval $(call fuzzer,062-pcie-int-pips,005-tilegrid,all)) +endif +ifeq ($(HAS_GTP),1) $(eval $(call fuzzer,063-gtp-common-conf,005-tilegrid,part)) $(eval $(call fuzzer,064-gtp-channel-conf,005-tilegrid,part)) $(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part)) @@ -194,7 +211,9 @@ endif endif endif $(eval $(call fuzzer,100-dsp-mskpat,005-tilegrid,all)) +ifneq ($(SKIP_DSP),1) $(eval $(call fuzzer,101-dsp-pips,005-tilegrid,all)) +endif quick: $(MAKE) QUICK=Y diff --git a/settings/zynq7/devices.yaml b/settings/zynq7/devices.yaml index e252aecb..29fac6f1 100644 --- a/settings/zynq7/devices.yaml +++ b/settings/zynq7/devices.yaml @@ -3,3 +3,11 @@ fabric: "xc7z020" "xc7z010": fabric: "xc7z010" +"xc7z030": + fabric: "xc7z030" +"xc7z035": + fabric: "xc7z045" +"xc7z045": + fabric: "xc7z045" +"xc7z100": + fabric: "xc7z100" diff --git a/settings/zynq7030.sh b/settings/zynq7030.sh new file mode 100644 index 00000000..3105a93e --- /dev/null +++ b/settings/zynq7030.sh @@ -0,0 +1,41 @@ +# Copyright (C) 2017-2024 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +export XRAY_DATABASE="zynq7" +export XRAY_PART="xc7z030fbg676-1" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + +# All CLB's in part, all BRAM's in part, all DSP's in part. +# This is the whole area of the device +export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X119Y199 RAMB18_X0Y0:RAMB18_X7Y79 RAMB36_X0Y0:RAMB36_X7Y39 DSP48_X0Y0:DSP48_X5Y79" #IOB_X0Y0:IOB_X1Y99 + +export XRAY_EXCLUDE_ROI_TILEGRID="" + +# left side has IOI3, right side doesn't +export XRAY_IOI3_TILES="LIOI3_X0Y9" +# This seems also very arbitrary? Value set according to 7010/7020, tested working on hardware +export XRAY_PS7_INT="INT_L_X18Y150" + +# These settings must remain in sync +# This is a subset of XRAY_ROI_TILEGRID, maybe one bank. +# Just using full device here w/o optimization +export XRAY_ROI="SLICE_X0Y0:SLICE_X119Y199 RAMB18_X0Y0:RAMB18_X7Y79 RAMB36_X0Y0:RAMB36_X7Y39 DSP48_X0Y0:DSP48_X5Y79 IOB_X0Y0:IOB_X0Y99 IOB_X1Y50:IOB_X1Y199" + +# This is the "Colume:" and "Row:" as shown in Vivado Tile Properties, using full device +export XRAY_ROI_GRID_X1="0" +export XRAY_ROI_GRID_X2="203" +export XRAY_ROI_GRID_Y1="105" +export XRAY_ROI_GRID_Y2="207" + +source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh + +env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py) +ENV_RET=$? +if [[ $ENV_RET != 0 ]] ; then + return $ENV_RET +fi +eval $env diff --git a/settings/zynq7045.sh b/settings/zynq7045.sh new file mode 100644 index 00000000..9ef99981 --- /dev/null +++ b/settings/zynq7045.sh @@ -0,0 +1,49 @@ +# Copyright (C) 2017-2024 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +export XRAY_DATABASE="zynq7" +export XRAY_PART="xc7z045ffg900-1" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + +# X0Y0:X0Y49 unbonded on even the largest footprint of xc7z045, this is handled inside fuzzers (005) + +# All CLB's in part, all BRAM's in part, all DSP's in part. +# This is the whole area of the device +export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X171Y349 RAMB18_X0Y0:RAMB18_X8Y139 RAMB36_X0Y0:RAMB36_X8Y69 DSP48_X0Y0:DSP48_X6Y139 IOB_X0Y50:IOB_X0Y249 IOB_X1Y200:IOB_X1Y349" + +export XRAY_EXCLUDE_ROI_TILEGRID="IOB_X0Y0:IOB_X0Y49" # This doesn't affect + +# left side has IOI3, right side doesn't +export XRAY_IOI3_TILES="LIOI3_X0Y9" #LIOI3_X0Y59 +# This seems also very arbitrary? Value set according to 7010/7020 +export XRAY_PS7_INT="INT_L_X18Y300" + +# These settings must remain in sync +# This is a subset of XRAY_ROI_TILEGRID, maybe one bank. +# Just using full device here w/o optimization +export XRAY_ROI="SLICE_X0Y0:SLICE_X171Y349 RAMB18_X0Y0:RAMB18_X8Y139 RAMB36_X0Y0:RAMB36_X8Y69 DSP48_X0Y0:DSP48_X6Y139 IOB_X0Y50:IOB_X0Y249 IOB_X1Y200:IOB_X1Y349" + +# This is the "Colume:" and "Row:" as shown in Vivado Tile Properties, using full device +export XRAY_ROI_GRID_X1="0" +export XRAY_ROI_GRID_X2="266" +export XRAY_ROI_GRID_Y1="1" +export XRAY_ROI_GRID_Y2="363" + +# Default pins work fine +#export XRAY_PIN_00=AA17 +#export XRAY_PIN_01=AB16 +#export XRAY_PIN_02=AB17 +#export XRAY_PIN_03=AC16 + +source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh + +env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py) +ENV_RET=$? +if [[ $ENV_RET != 0 ]] ; then + return $ENV_RET +fi +eval $env diff --git a/settings/zynq7100.sh b/settings/zynq7100.sh new file mode 100644 index 00000000..b3f9faf3 --- /dev/null +++ b/settings/zynq7100.sh @@ -0,0 +1,41 @@ +# Copyright (C) 2017-2024 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +export XRAY_DATABASE="zynq7" +export XRAY_PART="xc7z100ffg1156-1" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + +# All CLB's in part, all BRAM's in part, all DSP's in part. +# This is the whole area of the device +export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X213Y349 RAMB18_X0Y0:RAMB18_X11Y139 RAMB36_X0Y0:RAMB36_X11Y69 DSP48_X0Y0:DSP48_X14Y139" + +export XRAY_EXCLUDE_ROI_TILEGRID="" + +# left side has IOI3, right side doesn't +export XRAY_IOI3_TILES="LIOI3_X0Y9" +# This seems also very arbitrary? Value set according to 7010/7020 +export XRAY_PS7_INT="INT_L_X18Y300" + +# These settings must remain in sync +# This is a subset of XRAY_ROI_TILEGRID, maybe one bank. +# Just using full device here w/o optimization +export XRAY_ROI="SLICE_X0Y0:SLICE_X213Y349 RAMB18_X0Y0:RAMB18_X11Y139 RAMB36_X0Y0:RAMB36_X11Y69 DSP48_X0Y0:DSP48_X14Y139 IOB_X0Y0:IOB_X0Y249 IOB_X1Y200:IOB_X1Y349" + +# This is the "Colume:" and "Row:" as shown in Vivado Tile Properties, using full device +export XRAY_ROI_GRID_X1="0" +export XRAY_ROI_GRID_X2="352" +export XRAY_ROI_GRID_Y1="1" +export XRAY_ROI_GRID_Y2="363" + +source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh + +env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py) +ENV_RET=$? +if [[ $ENV_RET != 0 ]] ; then + return $ENV_RET +fi +eval $env