From d1cbcc2728ab8c979bbe25ea1b83434a7c31f5cb Mon Sep 17 00:00:00 2001
From: Hans Baier <hansfbaier@gmail.com>
Date: Tue, 3 Oct 2023 10:54:25 +0700
Subject: [PATCH] WIP state

---
 fuzzers/038a-cfg-pips/cfg_pip_list.tcl |  2 +-
 fuzzers/038a-cfg-pips/generate.tcl     |  1 +
 fuzzers/038a-cfg-pips/top.py           | 18 ++++++++++--------
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/fuzzers/038a-cfg-pips/cfg_pip_list.tcl b/fuzzers/038a-cfg-pips/cfg_pip_list.tcl
index 60536eab..2bc7f8c4 100644
--- a/fuzzers/038a-cfg-pips/cfg_pip_list.tcl
+++ b/fuzzers/038a-cfg-pips/cfg_pip_list.tcl
@@ -33,7 +33,7 @@ proc print_tile_pips {tile_type filename} {
                 continue
             }
 
-            if { true } {
+            if { [string match "*STARTUP*" $dst_node] } {
                 set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
                 if ![dict exists $pips $pip_string] {
                     puts $fp $pip_string
diff --git a/fuzzers/038a-cfg-pips/generate.tcl b/fuzzers/038a-cfg-pips/generate.tcl
index 490cb8cb..348b60b5 100644
--- a/fuzzers/038a-cfg-pips/generate.tcl
+++ b/fuzzers/038a-cfg-pips/generate.tcl
@@ -18,6 +18,7 @@ proc run {} {
 
     set_property IS_ENABLED 0 [get_drc_checks {REQP-21}]
     set_property IS_ENABLED 0 [get_drc_checks {REQP-25}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDCN-2}]
 
     set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
 
diff --git a/fuzzers/038a-cfg-pips/top.py b/fuzzers/038a-cfg-pips/top.py
index 466ff7c2..fb5dcb42 100644
--- a/fuzzers/038a-cfg-pips/top.py
+++ b/fuzzers/038a-cfg-pips/top.py
@@ -37,15 +37,17 @@ def print_site(ports, luts, site, site_type):
         for idx in range(0, width):
             rand = random.random()
 
-            if rand < 0.45:
-                source = "1'b0"
-            elif rand < 0.9:
-                source = "1'b1"
-            else:
-                source = luts.get_next_output_net()
+            # leave unconnected for some
+            if 0.5 <= rand:
+                if rand < 0.7:
+                    source = "1'b0"
+                elif rand < 0.9:
+                    source = "1'b1"
+                else:
+                    source = luts.get_next_output_net()
 
-            verilog_wires += "assign {}_{}[{}] = {};\n".format(
-                port, site, idx, source)
+                verilog_wires += "assign {}_{}[{}] = {};\n".format(
+                    port, site, idx, source)
 
         verilog_wires += "\n"