From ce926fc3597af0bf3ad29b2d33a4aa1f5330e5f1 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 30 Aug 2019 10:25:45 +0200 Subject: [PATCH] Added minitest which generates 32 differently delayed signals. Signed-off-by: Maciej Kurc --- minitests/idelay/README.md | 8 +- minitests/idelay/basys3.xdc | 8 +- minitests/idelay/basys3_idelay_const.v | 167 ++++++++++++++++++ ...asys3_idelay_ext.v => basys3_idelay_var.v} | 47 ++--- minitests/idelay/src/.idelay_calibrator.v.swp | Bin 12288 -> 0 bytes 5 files changed, 195 insertions(+), 35 deletions(-) create mode 100644 minitests/idelay/basys3_idelay_const.v rename minitests/idelay/{basys3_idelay_ext.v => basys3_idelay_var.v} (87%) delete mode 100644 minitests/idelay/src/.idelay_calibrator.v.swp diff --git a/minitests/idelay/README.md b/minitests/idelay/README.md index b67a447e..b4ba96a6 100644 --- a/minitests/idelay/README.md +++ b/minitests/idelay/README.md @@ -1,6 +1,6 @@ # Minitests for IDELAY -## 1. basys3_idelay_ext +## 1. basys3_idelay_var A design for Basys3 board. @@ -28,4 +28,8 @@ Consider the `JXADC` connector on the Basys3 board as seen when looking at the b - Pin7 - Delay signal input, connect to Pin8. - Pin8 - Signal output. Connect to Pin7. -**The oscilloscope must have bandwidth of at least 100MHz.** \ No newline at end of file +**The oscilloscope must have bandwidth of at least 100MHz.** + +## 1. basys3_idelay_const + +This design generates 32 independently shifted 50MHz square waves using constant delay IDELAY blocks. Delays between individual signals can be measured using an oscilloscope. Due to the fact that each delay step is about 100-150ps and the FPGA fabric + IOBs also introduce their own delays, actual delay values may be hard to measure. \ No newline at end of file diff --git a/minitests/idelay/basys3.xdc b/minitests/idelay/basys3.xdc index eb20c823..14348b73 100644 --- a/minitests/idelay/basys3.xdc +++ b/minitests/idelay/basys3.xdc @@ -68,12 +68,12 @@ set_property PACKAGE_PIN R18 [get_ports jc10] set_property PACKAGE_PIN J3 [get_ports xadc1_p] set_property PACKAGE_PIN L3 [get_ports xadc2_p] -#set_property PACKAGE_PIN M2 [get_ports xadc3_p] -#set_property PACKAGE_PIN N2 [get_ports xadc4_p] +set_property PACKAGE_PIN M2 [get_ports xadc3_p] +set_property PACKAGE_PIN N2 [get_ports xadc4_p] set_property PACKAGE_PIN K3 [get_ports xadc1_n] set_property PACKAGE_PIN M3 [get_ports xadc2_n] -#set_property PACKAGE_PIN M1 [get_ports xadc3_n] -#set_property PACKAGE_PIN N1 [get_ports xadc4_n] +set_property PACKAGE_PIN M1 [get_ports xadc3_n] +set_property PACKAGE_PIN N1 [get_ports xadc4_n] foreach port [get_ports] { set_property IOSTANDARD LVTTL $port diff --git a/minitests/idelay/basys3_idelay_const.v b/minitests/idelay/basys3_idelay_const.v new file mode 100644 index 00000000..72581384 --- /dev/null +++ b/minitests/idelay/basys3_idelay_const.v @@ -0,0 +1,167 @@ +`include "src/idelay_calibrator.v" + +`default_nettype none + +// ============================================================================ + +module top +( +input wire clk, + +input wire rx, +output wire tx, + +input wire [15:0] sw, +output wire [15:0] led, + +output wire ja1, +output wire ja2, +output wire ja3, +output wire ja4, +output wire ja7, +output wire ja8, +output wire ja9, +output wire ja10, + +output wire jb1, +output wire jb2, +output wire jb3, +output wire jb4, +output wire jb7, +output wire jb8, +output wire jb9, +output wire jb10, + +output wire jc1, +output wire jc2, +output wire jc3, +output wire jc4, +output wire jc7, +output wire jc8, +output wire jc9, +output wire jc10, + +output wire xadc1_p, +output wire xadc2_p, +output wire xadc3_p, +output wire xadc4_p, +output wire xadc1_n, +output wire xadc2_n, +output wire xadc3_n, +output wire xadc4_n +); + +// ============================================================================ +// Clock & reset +reg [3:0] rst_sr; + +initial rst_sr <= 4'hF; + +always @(posedge clk) + if (sw[0]) + rst_sr <= 4'hF; + else + rst_sr <= rst_sr >> 1; + +wire CLK = clk; +wire RST = rst_sr[0]; + +// ============================================================================ +// IDELAY calibrator +wire cal_rdy; + +idelay_calibrator cal +( +.refclk (CLK), +.rst (RST), +.rdy (cal_rdy) +); + +// ============================================================================ + +reg dly_in; +wire [31:0] dly_out; + +always @(posedge CLK) + if (RST) dly_in <= 0; + else dly_in <= ~dly_in; + +genvar i; +generate for (i=0; i<32; i=i+1) begin + + (* KEEP, DONT_TOUCH *) + IDELAYE2 # + ( + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (i), + .DELAY_SRC ("DATAIN") + ) + idelay + ( + .DATAIN (dly_in), + .DATAOUT (dly_out[i]) + ); + +end endgenerate + +// ============================================================================ +// I/O connections +reg [23:0] heartbeat_cnt; + +always @(posedge CLK) + heartbeat_cnt <= heartbeat_cnt + 1; + +assign led[ 0] = heartbeat_cnt[23]; +assign led[ 1] = cal_rdy; +assign led[ 2] = 1'b0; +assign led[ 3] = 1'b0; +assign led[ 4] = 1'b0; +assign led[ 5] = 1'b0; +assign led[ 6] = 1'b0; +assign led[ 7] = 1'b0; +assign led[ 8] = 1'b0; +assign led[ 9] = 1'b0; +assign led[10] = 1'b0; +assign led[11] = 1'b0; +assign led[12] = 1'b0; +assign led[13] = 1'b0; +assign led[14] = 1'b0; +assign led[15] = 1'b0; + +assign ja1 = dly_out[ 0]; +assign ja2 = dly_out[ 1]; +assign ja3 = dly_out[ 2]; +assign ja4 = dly_out[ 3]; +assign ja7 = dly_out[ 4]; +assign ja8 = dly_out[ 5]; +assign ja9 = dly_out[ 6]; +assign ja10 = dly_out[ 7]; + +assign jb1 = dly_out[ 8]; +assign jb2 = dly_out[ 9]; +assign jb3 = dly_out[10]; +assign jb4 = dly_out[11]; +assign jb7 = dly_out[12]; +assign jb8 = dly_out[13]; +assign jb9 = dly_out[14]; +assign jb10 = dly_out[15]; + +assign jc1 = dly_out[16]; +assign jc2 = dly_out[17]; +assign jc3 = dly_out[18]; +assign jc4 = dly_out[19]; +assign jc7 = dly_out[20]; +assign jc8 = dly_out[21]; +assign jc9 = dly_out[22]; +assign jc10 = dly_out[23]; + +assign xadc1_p = dly_out[24]; +assign xadc2_p = dly_out[25]; +assign xadc3_p = dly_out[26]; +assign xadc4_p = dly_out[27]; +assign xadc1_n = dly_out[28]; +assign xadc2_n = dly_out[29]; +assign xadc3_n = dly_out[30]; +assign xadc4_n = dly_out[31]; + +endmodule diff --git a/minitests/idelay/basys3_idelay_ext.v b/minitests/idelay/basys3_idelay_var.v similarity index 87% rename from minitests/idelay/basys3_idelay_ext.v rename to minitests/idelay/basys3_idelay_var.v index 3ae1e8f4..d6f08c07 100644 --- a/minitests/idelay/basys3_idelay_ext.v +++ b/minitests/idelay/basys3_idelay_var.v @@ -14,37 +14,41 @@ output wire tx, input wire [15:0] sw, output wire [15:0] led, -output wire ja1, -output wire ja2, -output wire ja3, -output wire ja4, +input wire ja1, +input wire ja2, +input wire ja3, +input wire ja4, input wire ja7, input wire ja8, input wire ja9, input wire ja10, -output wire jb1, -output wire jb2, -output wire jb3, -output wire jb4, +input wire jb1, +input wire jb2, +input wire jb3, +input wire jb4, input wire jb7, input wire jb8, input wire jb9, input wire jb10, -output wire jc1, -output wire jc2, -output wire jc3, -output wire jc4, +input wire jc1, +input wire jc2, +input wire jc3, +input wire jc4, input wire jc7, input wire jc8, input wire jc9, input wire jc10, output wire xadc1_p, -input wire xadc1_n, output wire xadc2_p, -output wire xadc2_n +input wire xadc3_p, +input wire xadc4_p, +input wire xadc1_n, +output wire xadc2_n, +input wire xadc3_n, +input wire xadc4_n ); // ============================================================================ @@ -166,21 +170,6 @@ assign led[13] = dly_delay_out[2]; assign led[14] = dly_delay_out[3]; assign led[15] = dly_delay_out[4]; -assign ja1 = 1'b0; -assign ja2 = 1'b0; -assign ja3 = 1'b0; -assign ja4 = 1'b0; - -assign jb1 = 1'b0; -assign jb2 = 1'b0; -assign jb3 = 1'b0; -assign jb4 = 1'b0; - -assign jc1 = 1'b0; -assign jc2 = 1'b0; -assign jc3 = 1'b0; -assign jc4 = 1'b0; - assign xadc2_p = O; assign xadc2_n = O; assign xadc1_p = dly_out; diff --git a/minitests/idelay/src/.idelay_calibrator.v.swp b/minitests/idelay/src/.idelay_calibrator.v.swp deleted file mode 100644 index 136221ebe2220fa70139068e281a10e41b0e24d8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12288 zcmeI2&rcIU6vrQ26c9Cf)nq7_mR~KJAh9+POO1qT2^13~qz=2&va;Q6W~V}9#OTfc zKohxn*2Eh({{auilSU85c+i9YfET~JU8H#7!bS2X`DAxqUw7tx@_N{GRx`I}Zi>mV z3}Kum>ibYz>Fv4Gy={o<>rHKi@dHMbH#(O;AdR-7#Pqys_(8hn`!!dMHuSwsEnB+pgg-pj=K2}xBT}LEIGt-6Q)Kb1YUli?A#g=h3C5Oapp)fZhrc1ZVm2zn@ ze`7=xOL>tK3p3?HCA=L<;T0w=_8t(0Sf03?S!ritlMqt$y&4`BC?jghQ_&G^k=&Zdc!8+;T1;u< zY>G=lT9&VE2g$}4W=#oO8X2r9g{>XBSG0=XG>xVaQ5oo#b|qM-)Q)Q<5e)51H#89D z#>s&hiL#Mg*fdHbqg~+sw5Y|9iL|)w!g4#hB}pl2NGYoLkZ9K6#W5_VmGn?