From 7bd13efdcb546556f5affc07e00e9124418e6d25 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 10 Dec 2019 15:21:28 +0100 Subject: [PATCH 1/6] WIP Signed-off-by: Maciej Kurc --- .../041-clk-hrow-pips/clk_hrow_pip_list.tcl | 5 ---- fuzzers/041-clk-hrow-pips/top.py | 25 +++++++++++++++++++ 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/fuzzers/041-clk-hrow-pips/clk_hrow_pip_list.tcl b/fuzzers/041-clk-hrow-pips/clk_hrow_pip_list.tcl index 597872ad..791a369d 100644 --- a/fuzzers/041-clk-hrow-pips/clk_hrow_pip_list.tcl +++ b/fuzzers/041-clk-hrow-pips/clk_hrow_pip_list.tcl @@ -28,11 +28,6 @@ proc print_tile_pips {tile_type filename} { continue } - # TODO: Support CLK sources from PS7 hardblock - if [string match *PSS_HCLK* $src_node] { - continue - } - if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} { set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" if ![dict exists $pips $pip_string] { diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py index 472eacd8..ed38a7a7 100644 --- a/fuzzers/041-clk-hrow-pips/top.py +++ b/fuzzers/041-clk-hrow-pips/top.py @@ -314,6 +314,7 @@ module top(); site_to_cmt = dict(read_site_to_cmt()) + is_zynq = os.getenv('XRAY_DATABASE') == 'zynq7' clock_sources = ClockSources() # To ensure that all left or right sources are used, sometimes only MMCM/PLL @@ -531,6 +532,30 @@ module top(); break break + if is_zynq: + for loc, _, site in gen_sites('PS7'): + print(""" + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + PS7 ps7_{site} ( + .FCLKCLK({fclk3, fclk2, fclk1, fclk0}), + .TESTPLLCLKOUT({testpllclkout2, testpllclkout1, testpllclkout0}), + .TESTPLLNEWCLK({testpllnewclk2, testpllnewclk1, testpllnewclk0}), + ); + """.format( + site=site, + fclk0=, + fclk1=, + fclk2=, + fclk3=, + testpllclkout2=, + testpllclkout1=, + testpllclkout0=, + testpllnewclk2=, + testpllnewclk1=, + testpllnewclk0=, + )) + + for l in luts.create_wires_and_luts(): print(l) From 6086e6d6f5ccfa074e14b58c937bd98fe82dd7c4 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 11 Dec 2019 16:25:45 +0100 Subject: [PATCH 2/6] Modified fuzzer 041 to solve Zynq PS7 FCLK clocks. Signed-off-by: Maciej Kurc --- fuzzers/041-clk-hrow-pips/Makefile | 13 ++- fuzzers/041-clk-hrow-pips/generate.tcl | 12 ++- fuzzers/041-clk-hrow-pips/output_cmt.tcl | 2 +- .../041-clk-hrow-pips/output_pss_clocks.tcl | 23 +++++ fuzzers/041-clk-hrow-pips/top.py | 99 +++++++++++++------ 5 files changed, 116 insertions(+), 33 deletions(-) create mode 100644 fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl diff --git a/fuzzers/041-clk-hrow-pips/Makefile b/fuzzers/041-clk-hrow-pips/Makefile index 5a370e1b..8612c58a 100644 --- a/fuzzers/041-clk-hrow-pips/Makefile +++ b/fuzzers/041-clk-hrow-pips/Makefile @@ -9,7 +9,7 @@ N = 50 # These PIPs all appear to be either a 2 bit solutions. SEGMATCH_FLAGS=-c 2 -SPECIMENS_DEPS=build/cmt_regions.csv +SPECIMENS_DEPS=build/dump.ok A_PIPLIST=clk_hrow_bot_r.txt include ../pip_loop.mk @@ -37,9 +37,18 @@ database: build/segbits_clk_hrow_bot_r.rdb build/segbits_clk_hrow_top_r.rdb XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow_bot_r.db XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow_top_r.db -build/cmt_regions.csv: output_cmt.tcl +ifeq (${XRAY_DATABASE}, zynq7) +build/dump.ok: output_cmt.tcl output_pss_clocks.tcl mkdir -p build cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl + cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_pss_clocks.tcl + touch build/dump.ok +else +build/dump.ok: output_cmt.tcl + mkdir -p build + cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl + touch build/dump.ok +endif generate: $(SPECIMENS_OK) diff --git a/fuzzers/041-clk-hrow-pips/generate.tcl b/fuzzers/041-clk-hrow-pips/generate.tcl index 5f9277e1..21c4ffb9 100644 --- a/fuzzers/041-clk-hrow-pips/generate.tcl +++ b/fuzzers/041-clk-hrow-pips/generate.tcl @@ -246,9 +246,17 @@ proc run {} { set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets] place_design - route_design + + puts "Routing design #1" + route_design -directive Quick + write_checkpoint -force design_initially_routed.dcp + + puts "Routing TODOs" route_todo - route_design + write_checkpoint -force design_todo_routed.dcp + + puts "Routing design #2" + route_design -directive Quick write_checkpoint -force design.dcp write_bitstream -force design.bit diff --git a/fuzzers/041-clk-hrow-pips/output_cmt.tcl b/fuzzers/041-clk-hrow-pips/output_cmt.tcl index 06aba163..070e5884 100644 --- a/fuzzers/041-clk-hrow-pips/output_cmt.tcl +++ b/fuzzers/041-clk-hrow-pips/output_cmt.tcl @@ -3,7 +3,7 @@ set_property design_mode PinPlanning [current_fileset] open_io_design -name io_1 set fp [open "cmt_regions.csv" "w"] -foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR} { +foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR PS7} { foreach site [get_sites -filter "SITE_TYPE == $site_type"] { puts $fp "$site,[get_property CLOCK_REGION $site]" } diff --git a/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl b/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl new file mode 100644 index 00000000..22e26e72 --- /dev/null +++ b/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl @@ -0,0 +1,23 @@ +create_project -force -part $::env(XRAY_PART) design design +set_property design_mode PinPlanning [current_fileset] +open_io_design -name io_1 + +set fp [open "pss_clocks.csv" "w"] +puts $fp "pin,tile" + +# List all PSS_HCLK wires +set pss_clk_wires [get_wires *PSS_HCLK* -of_objects [get_tiles PSS*]] +foreach wire $pss_clk_wires { + # Get PIPs that mention the wire inside a CLK_HROW tile. + set pips [get_pips CLK_HROW_* -of_objects [get_nodes -of_objects $wire]] + # Get the CLK_HROW tile. + set tile [get_tiles -of_objects [lindex $pips 0]] + + # Get uphill PIP, parse its name to get the PS7 wire name. + set pip [get_pips -uphill -of_objects $wire] + set pin [lindex [split [lindex [split $pip "."] 1] "-"] 0] + + puts $fp "$pin,$tile" +} + +close $fp diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py index ed38a7a7..dd991374 100644 --- a/fuzzers/041-clk-hrow-pips/top.py +++ b/fuzzers/041-clk-hrow-pips/top.py @@ -5,14 +5,19 @@ import re random.seed(int(os.getenv("SEED"), 16)) from prjxray import util from prjxray import verilog +from prjxray.grid_types import GridLoc from prjxray.db import Database from prjxray.lut_maker import LutMaker from io import StringIO +import csv +import sys CMT_XY_FUN = util.create_xy_fun(prefix='') BUFGCTRL_XY_FUN = util.create_xy_fun('BUFGCTRL_') BUFHCE_XY_FUN = util.create_xy_fun('BUFHCE_') +def eprint(*args, **kwargs): + print(*args, file=sys.stderr, **kwargs) def gen_sites(desired_site_type): db = Database(util.get_db_root()) @@ -41,6 +46,10 @@ def gen_bufhce_sites(): if sites: yield tile_name, sorted(sites) +def get_cmt_loc(cmt_tile_name): + db = Database(util.get_db_root()) + grid = db.grid() + return grid.loc_of_tilename(cmt_tile_name) def read_site_to_cmt(): """ Yields clock sources and which CMT they route within. """ @@ -50,6 +59,11 @@ def read_site_to_cmt(): site, cmt = l.strip().split(',') yield (site, cmt) +def read_pss_clocks(): + with open(os.path.join(os.getenv('FUZDIR'), 'build', + 'pss_clocks.csv')) as f: + for l in csv.DictReader(f): + yield l class ClockSources(object): """ Class for tracking clock sources. @@ -147,7 +161,7 @@ class ClockSources(object): if src_loc is None: continue if src_loc.grid_y <= loc.grid_y: - bufg_sources.extend(cmt_sources) + bufg_sources.extend(cmt_sources) elif bottom: for src_loc, cmt_sources in self.sources_by_loc.items(): if src_loc is None: @@ -305,18 +319,23 @@ def main(): PLLE2_ADV BUFGCTRL Local INT connect - + PS7 (Zynq) """ print(''' +// SEED={} module top(); - ''') + '''.format(os.getenv('SEED'))) - site_to_cmt = dict(read_site_to_cmt()) is_zynq = os.getenv('XRAY_DATABASE') == 'zynq7' clock_sources = ClockSources() + site_to_cmt = dict(read_site_to_cmt()) + + if is_zynq: + pss_clocks = list(read_pss_clocks()) + # To ensure that all left or right sources are used, sometimes only MMCM/PLL # sources are allowed. The force of ODD/EVEN/BOTH further biases the # clock sources to the left or right column inputs. @@ -427,6 +446,42 @@ module top(); .O(O_{site}) );""".format(site=site)) + if is_zynq: + + clocks = [ + "PSS_FCLKCLK0", + "PSS_FCLKCLK1", + "PSS_FCLKCLK2", + "PSS_FCLKCLK3", + ] + + loc, _, site = next(gen_sites('PS7')) + + print("") + + for wire in clocks: + cmt = site_to_cmt[site] + cmt_tile = [d["tile"] for d in pss_clocks if d["pin"] == wire][0] + cmt_loc = get_cmt_loc(cmt_tile) + + clock_sources.add_clock_source(wire, cmt, cmt_loc) + print(" wire {};".format(wire)) + + print(""" + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + PS7 ps7_{site} ( + .FCLKCLK({{{fclk3}, {fclk2}, {fclk1}, {fclk0}}}) + ); + """.format( + site=site, + fclk0=clocks[0], + fclk1=clocks[1], + fclk2=clocks[2], + fclk3=clocks[3] + )) + + used_pss_clocks = set() + luts = LutMaker() bufhs = StringIO() bufgs = StringIO() @@ -497,6 +552,12 @@ module top(); if random.random() > .05: wire_name = clock_sources.get_random_source(site_to_cmt[site]) + if wire_name is not None and wire_name.startswith("PSS"): + if wire_name not in used_pss_clocks: + used_pss_clocks.add(wire_name) + else: + wire_name = None + if wire_name is None: continue @@ -532,28 +593,6 @@ module top(); break break - if is_zynq: - for loc, _, site in gen_sites('PS7'): - print(""" - (* KEEP, DONT_TOUCH, LOC = "{site}" *) - PS7 ps7_{site} ( - .FCLKCLK({fclk3, fclk2, fclk1, fclk0}), - .TESTPLLCLKOUT({testpllclkout2, testpllclkout1, testpllclkout0}), - .TESTPLLNEWCLK({testpllnewclk2, testpllnewclk1, testpllnewclk0}), - ); - """.format( - site=site, - fclk0=, - fclk1=, - fclk2=, - fclk3=, - testpllclkout2=, - testpllclkout1=, - testpllclkout0=, - testpllnewclk2=, - testpllnewclk1=, - testpllnewclk0=, - )) for l in luts.create_wires_and_luts(): @@ -569,7 +608,9 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 1, used_only) - if wire_name is not None: + if wire_name is not None and wire_name not in used_pss_clocks: + if wire_name.startswith("PSS"): + used_pss_clocks.add(wire_name) print( """ assign I1_{site} = {wire_name};""".format( @@ -580,7 +621,9 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 0, used_only) - if wire_name is not None: + if wire_name is not None and wire_name not in used_pss_clocks: + if wire_name.startswith("PSS"): + used_pss_clocks.add(wire_name) print( """ assign I0_{site} = {wire_name};""".format( From fb65464c42edc7d8596d0b7ab71474e86b263133 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 11 Dec 2019 19:05:04 +0100 Subject: [PATCH 3/6] A little hacky but working version. Signed-off-by: Maciej Kurc --- fuzzers/041-clk-hrow-pips/output_cmt.tcl | 2 +- fuzzers/041-clk-hrow-pips/top.py | 23 +++++++++-------------- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/fuzzers/041-clk-hrow-pips/output_cmt.tcl b/fuzzers/041-clk-hrow-pips/output_cmt.tcl index 070e5884..06aba163 100644 --- a/fuzzers/041-clk-hrow-pips/output_cmt.tcl +++ b/fuzzers/041-clk-hrow-pips/output_cmt.tcl @@ -3,7 +3,7 @@ set_property design_mode PinPlanning [current_fileset] open_io_design -name io_1 set fp [open "cmt_regions.csv" "w"] -foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR PS7} { +foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR} { foreach site [get_sites -filter "SITE_TYPE == $site_type"] { puts $fp "$site,[get_property CLOCK_REGION $site]" } diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py index dd991374..05c4e3ff 100644 --- a/fuzzers/041-clk-hrow-pips/top.py +++ b/fuzzers/041-clk-hrow-pips/top.py @@ -460,11 +460,11 @@ module top(); print("") for wire in clocks: - cmt = site_to_cmt[site] cmt_tile = [d["tile"] for d in pss_clocks if d["pin"] == wire][0] cmt_loc = get_cmt_loc(cmt_tile) - clock_sources.add_clock_source(wire, cmt, cmt_loc) + # FIXME: HACK + clock_sources.add_clock_source(wire, "X0Y0", cmt_loc) print(" wire {};".format(wire)) print(""" @@ -480,8 +480,6 @@ module top(); fclk3=clocks[3] )) - used_pss_clocks = set() - luts = LutMaker() bufhs = StringIO() bufgs = StringIO() @@ -552,11 +550,10 @@ module top(); if random.random() > .05: wire_name = clock_sources.get_random_source(site_to_cmt[site]) + # FIXME: HACK if wire_name is not None and wire_name.startswith("PSS"): - if wire_name not in used_pss_clocks: - used_pss_clocks.add(wire_name) - else: - wire_name = None + if "BOT" not in tile_name: + continue if wire_name is None: continue @@ -608,9 +605,8 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 1, used_only) - if wire_name is not None and wire_name not in used_pss_clocks: - if wire_name.startswith("PSS"): - used_pss_clocks.add(wire_name) + + if wire_name is not None: print( """ assign I1_{site} = {wire_name};""".format( @@ -621,9 +617,8 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 0, used_only) - if wire_name is not None and wire_name not in used_pss_clocks: - if wire_name.startswith("PSS"): - used_pss_clocks.add(wire_name) + + if wire_name is not None: print( """ assign I0_{site} = {wire_name};""".format( From 24ccfb3bb52fe0de88c8909705921a255db791f0 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 11 Dec 2019 21:43:01 +0100 Subject: [PATCH 4/6] Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources. Signed-off-by: Maciej Kurc --- fuzzers/041-clk-hrow-pips/generate.tcl | 8 --- .../041-clk-hrow-pips/output_pss_clocks.tcl | 32 +++++++-- fuzzers/041-clk-hrow-pips/top.py | 68 +++++++++++-------- 3 files changed, 65 insertions(+), 43 deletions(-) diff --git a/fuzzers/041-clk-hrow-pips/generate.tcl b/fuzzers/041-clk-hrow-pips/generate.tcl index 21c4ffb9..3b040dfa 100644 --- a/fuzzers/041-clk-hrow-pips/generate.tcl +++ b/fuzzers/041-clk-hrow-pips/generate.tcl @@ -246,16 +246,8 @@ proc run {} { set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets] place_design - - puts "Routing design #1" route_design -directive Quick - write_checkpoint -force design_initially_routed.dcp - - puts "Routing TODOs" route_todo - write_checkpoint -force design_todo_routed.dcp - - puts "Routing design #2" route_design -directive Quick write_checkpoint -force design.dcp diff --git a/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl b/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl index 22e26e72..8aacf2d9 100644 --- a/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl +++ b/fuzzers/041-clk-hrow-pips/output_pss_clocks.tcl @@ -3,21 +3,39 @@ set_property design_mode PinPlanning [current_fileset] open_io_design -name io_1 set fp [open "pss_clocks.csv" "w"] -puts $fp "pin,tile" +puts $fp "pin,wire,tile,clock_regions" # List all PSS_HCLK wires set pss_clk_wires [get_wires *PSS_HCLK* -of_objects [get_tiles PSS*]] foreach wire $pss_clk_wires { - # Get PIPs that mention the wire inside a CLK_HROW tile. - set pips [get_pips CLK_HROW_* -of_objects [get_nodes -of_objects $wire]] - # Get the CLK_HROW tile. - set tile [get_tiles -of_objects [lindex $pips 0]] - # Get uphill PIP, parse its name to get the PS7 wire name. + # Get PIPs that mention the wire inside a CLK_HROW tile. Take the first one. + set pips [get_pips CLK_HROW_* -of_objects [get_nodes -of_objects $wire]] + set pip [lindex $pips 0] + + # Get the CLK_HROW tile. + set tile [get_tiles -of_objects $pip] + + # Get the name of the input wire of the CLK_HROW tile. This is different + # than the name of the PSS clock wire. Do it by parsing the PIP name + set cmt_wire [lindex [split [lindex [split $pip "-"] 0] "."] 1] + + # Get clock regions of the tile. CLK_HROW tiles span two regions. + set regions [dict create] + foreach site [get_sites -of_objects $tile] { + set region [get_property CLOCK_REGION $site] + dict incr regions $region + } + + set regions [dict keys $regions] + + # Get uphill PIP, parse its name to get the PS7 wire name. This will be + # actually the wire of the PSS tile but the important part of the name + # is the same. set pip [get_pips -uphill -of_objects $wire] set pin [lindex [split [lindex [split $pip "."] 1] "-"] 0] - puts $fp "$pin,$tile" + puts $fp "$pin,$cmt_wire,$tile,$regions" } close $fp diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py index 05c4e3ff..effc95f0 100644 --- a/fuzzers/041-clk-hrow-pips/top.py +++ b/fuzzers/041-clk-hrow-pips/top.py @@ -16,9 +16,11 @@ CMT_XY_FUN = util.create_xy_fun(prefix='') BUFGCTRL_XY_FUN = util.create_xy_fun('BUFGCTRL_') BUFHCE_XY_FUN = util.create_xy_fun('BUFHCE_') + def eprint(*args, **kwargs): print(*args, file=sys.stderr, **kwargs) + def gen_sites(desired_site_type): db = Database(util.get_db_root()) grid = db.grid() @@ -46,11 +48,13 @@ def gen_bufhce_sites(): if sites: yield tile_name, sorted(sites) + def get_cmt_loc(cmt_tile_name): db = Database(util.get_db_root()) grid = db.grid() return grid.loc_of_tilename(cmt_tile_name) + def read_site_to_cmt(): """ Yields clock sources and which CMT they route within. """ with open(os.path.join(os.getenv('FUZDIR'), 'build', @@ -59,12 +63,14 @@ def read_site_to_cmt(): site, cmt = l.strip().split(',') yield (site, cmt) + def read_pss_clocks(): with open(os.path.join(os.getenv('FUZDIR'), 'build', - 'pss_clocks.csv')) as f: + 'pss_clocks.csv')) as f: for l in csv.DictReader(f): yield l + class ClockSources(object): """ Class for tracking clock sources. @@ -161,7 +167,7 @@ class ClockSources(object): if src_loc is None: continue if src_loc.grid_y <= loc.grid_y: - bufg_sources.extend(cmt_sources) + bufg_sources.extend(cmt_sources) elif bottom: for src_loc, cmt_sources in self.sources_by_loc.items(): if src_loc is None: @@ -327,7 +333,6 @@ def main(): module top(); '''.format(os.getenv('SEED'))) - is_zynq = os.getenv('XRAY_DATABASE') == 'zynq7' clock_sources = ClockSources() @@ -448,37 +453,54 @@ module top(); if is_zynq: + # FCLK clocks. Those are generated by the PS and go directly to one of + # the CLK_HROW tile. clocks = [ - "PSS_FCLKCLK0", - "PSS_FCLKCLK1", - "PSS_FCLKCLK2", - "PSS_FCLKCLK3", + "PSS_FCLKCLK0", + "PSS_FCLKCLK1", + "PSS_FCLKCLK2", + "PSS_FCLKCLK3", ] loc, _, site = next(gen_sites('PS7')) print("") - + + # Add clock sources and generate wires for wire in clocks: - cmt_tile = [d["tile"] for d in pss_clocks if d["pin"] == wire][0] + clock_info = [d for d in pss_clocks if d["pin"] == wire][0] + + # CMT tile + cmt_tile = clock_info["tile"] cmt_loc = get_cmt_loc(cmt_tile) - # FIXME: HACK - clock_sources.add_clock_source(wire, "X0Y0", cmt_loc) + # Add only if the input wire is in the todo list + dsts = [k for k, v in todos.items() if clock_info["wire"] in v] + if len(dsts) > 0: + + # Wire source clock region. The PS7 is always left of the + # CLK_HROW tile, but it does not matter here. + regions = clock_info["clock_regions"].split() + regions = sorted([(int(r[1]), int(r[3])) for r in regions]) + + # Add the clock source + cmt = "X{}Y{}".format(regions[0][0], regions[0][1]) + clock_sources.add_clock_source(wire, cmt, cmt_loc) + print(" wire {};".format(wire)) - print(""" + print( + """ (* KEEP, DONT_TOUCH, LOC = "{site}" *) PS7 ps7_{site} ( .FCLKCLK({{{fclk3}, {fclk2}, {fclk1}, {fclk0}}}) ); """.format( - site=site, - fclk0=clocks[0], - fclk1=clocks[1], - fclk2=clocks[2], - fclk3=clocks[3] - )) + site=site, + fclk0=clocks[0], + fclk1=clocks[1], + fclk2=clocks[2], + fclk3=clocks[3])) luts = LutMaker() bufhs = StringIO() @@ -550,11 +572,6 @@ module top(); if random.random() > .05: wire_name = clock_sources.get_random_source(site_to_cmt[site]) - # FIXME: HACK - if wire_name is not None and wire_name.startswith("PSS"): - if "BOT" not in tile_name: - continue - if wire_name is None: continue @@ -590,8 +607,6 @@ module top(); break break - - for l in luts.create_wires_and_luts(): print(l) @@ -605,7 +620,6 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 1, used_only) - if wire_name is not None: print( """ @@ -617,7 +631,6 @@ module top(); if random.randint(0, 1): wire_name = clock_sources.get_bufg_source( loc, tile_type, site, todos, 0, used_only) - if wire_name is not None: print( """ @@ -628,6 +641,5 @@ module top(); print("endmodule") - if __name__ == '__main__': main() From 0507f9234532e7b521a1dd5150e159342e5ec27f Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 12 Dec 2019 09:31:59 +0100 Subject: [PATCH 5/6] Ran make format Signed-off-by: Maciej Kurc --- fuzzers/041-clk-hrow-pips/top.py | 1 + 1 file changed, 1 insertion(+) diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py index effc95f0..3993fd03 100644 --- a/fuzzers/041-clk-hrow-pips/top.py +++ b/fuzzers/041-clk-hrow-pips/top.py @@ -641,5 +641,6 @@ module top(); print("endmodule") + if __name__ == '__main__': main() From 810473ef46f0072a5f7fb2e68b216ba6e3355fab Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 12 Dec 2019 17:10:25 +0100 Subject: [PATCH 6/6] Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7 Signed-off-by: Maciej Kurc --- fuzzers/000-init-db/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fuzzers/000-init-db/Makefile b/fuzzers/000-init-db/Makefile index d1eec21c..60975cb2 100644 --- a/fuzzers/000-init-db/Makefile +++ b/fuzzers/000-init-db/Makefile @@ -39,12 +39,14 @@ DB_SIMPLE=\ $(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) \ segbits_cmt_top_l_upper_t \ segbits_cmt_top_r_upper_t \ - segbits_lioi3 \ segbits_rioi3 \ - segbits_liob33 \ segbits_riob33 \ segbits_hclk_ioi3 \ +ifneq (${XRAY_DATABASE}, zynq7) +DB_SIMPLE += segbits_lioi3 segbits_liob33 +endif + BLOCK_RAM_EXTRA_FOR=\ mask_bram \ segbits_bram