diff --git a/minitests/lvb_long_mux/.gitignore b/minitests/lvb_long_mux/.gitignore
new file mode 100644
index 00000000..c2b91364
--- /dev/null
+++ b/minitests/lvb_long_mux/.gitignore
@@ -0,0 +1,10 @@
+/.Xil
+/design/
+/design_a.bit
+/design_a.bits
+/design_a.dcp
+/design_b.bit
+/design_b.bits
+/design_b.dcp
+/usage_statistics_webtalk.*
+/vivado*
diff --git a/minitests/lvb_long_mux/runme.sh b/minitests/lvb_long_mux/runme.sh
new file mode 100644
index 00000000..16925952
--- /dev/null
+++ b/minitests/lvb_long_mux/runme.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+set -ex
+vivado -mode batch -source runme.tcl
+../../tools/bitread -F $XRAY_ROI_FRAMES -o design_a.bits -zy design_a.bit
+../../tools/bitread -F $XRAY_ROI_FRAMES -o design_b.bits -zy design_b.bit
+python3 ../../utils/segprint.py design_a.bits INT_L_X12Y132 INT_L_X14Y132 INT_L_X16Y132
+python3 ../../utils/segprint.py design_b.bits INT_L_X12Y132 INT_L_X14Y132 INT_L_X16Y132
diff --git a/minitests/lvb_long_mux/runme.tcl b/minitests/lvb_long_mux/runme.tcl
new file mode 100644
index 00000000..fbcf472c
--- /dev/null
+++ b/minitests/lvb_long_mux/runme.tcl
@@ -0,0 +1,65 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+
+create_pblock roi
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+source ../../utils/utils.tcl
+
+# ----------------------------------------------------------
+
+set_property FIXED_ROUTE {} [get_nets o_OBUF]
+route_design -unroute
+
+route_via o_OBUF {
+	INT_L_X12Y144/LVB_L12 INT_L_X12Y132/LVB_L12
+
+	INT_L_X12Y120/SS6BEG2
+	INT_L_X14Y120/NN6END3
+
+	INT_L_X14Y132/LVB_L12 INT_L_X14Y144/LVB_L12
+	INT_L_X16Y144/LVB_L12 INT_L_X16Y132/LVB_L12
+}
+
+# ----------------------------------------------------------
+
+route_design
+write_checkpoint -force design_a.dcp
+write_bitstream -force design_a.bit
+
+# ----------------------------------------------------------
+
+set_property FIXED_ROUTE {} [get_nets o_OBUF]
+route_design -unroute
+
+route_via o_OBUF {
+	INT_L_X12Y120/NN6END3
+
+	INT_L_X12Y132/LVB_L12 INT_L_X12Y144/LVB_L12
+
+	INT_L_X14Y144/LVB_L12 INT_L_X14Y132/LVB_L12
+
+	INT_L_X14Y120/SS6BEG2
+	INT_L_X16Y120/NN6END3
+
+	INT_L_X16Y132/LVB_L12 INT_L_X16Y144/LVB_L12
+
+	INT_L_X16Y144/EE4BEG2
+}
+
+# ----------------------------------------------------------
+
+route_design
+write_checkpoint -force design_b.dcp
+write_bitstream -force design_b.bit
+
diff --git a/minitests/lvb_long_mux/top.v b/minitests/lvb_long_mux/top.v
new file mode 100644
index 00000000..c0e91c58
--- /dev/null
+++ b/minitests/lvb_long_mux/top.v
@@ -0,0 +1,3 @@
+module top (input i, output o);
+	assign o = i;
+endmodule
diff --git a/utils/segprint.py b/utils/segprint.py
index 7fadb15b..4f448c13 100644
--- a/utils/segprint.py
+++ b/utils/segprint.py
@@ -24,11 +24,45 @@ with open(sys.argv[1], "r") as f:
 
         bitdata[frame][wordidx].add(bitidx)
 
-for arg in sys.argv[2:]:
-    if arg in grid["tiles"]:
-        segname = grid["tiles"][arg]["segment"]
-    else:
-        segname = arg
+def handle_segment(segname):
+    if ":" in segname:
+        seg1, seg2 = segname.split(":")
+
+        if seg1 in grid["tiles"]:
+            seg1 = grid["tiles"][seg1]["segment"]
+
+        if seg2 in grid["tiles"]:
+            seg2 = grid["tiles"][seg2]["segment"]
+
+        seginfo1 = grid["segments"][seg1]
+        seginfo2 = grid["segments"][seg2]
+
+        frame1 = int(seginfo1["baseaddr"][0], 16)
+        word1 = int(seginfo1["baseaddr"][1])
+
+        frame2 = int(seginfo2["baseaddr"][0], 16)
+        word2 = int(seginfo2["baseaddr"][1])
+
+        if frame1 > frame2:
+            frame1, frame2 = frame2, frame1
+
+        if word1 > word2:
+            word1, word2 = word2, word1
+
+        segs = list()
+
+        for seg, seginfo in sorted(grid["segments"].items()):
+            frame = int(seginfo["baseaddr"][0], 16)
+            word = int(seginfo["baseaddr"][1])
+            if frame1 <= frame <= frame2 and word1 <= word <= word2:
+                segs.append((frame, word, seg))
+
+        for _, _, seg in sorted(segs):
+            handle_segment(seg)
+        return
+
+    if segname in grid["tiles"]:
+        segname = grid["tiles"][segname]["segment"]
 
     print()
     print("seg %s" % segname)
@@ -49,3 +83,6 @@ for arg in sys.argv[2:]:
             for bitidx in bitdata[frame][wordidx]:
                 print("bit %02d_%02d" % (frame - baseframe, 32*(wordidx - basewordidx) + bitidx))
 
+for arg in sys.argv[2:]:
+    handle_segment(arg)
+
diff --git a/utils/utils.tcl b/utils/utils.tcl
index 75da3e01..d0f80a1e 100644
--- a/utils/utils.tcl
+++ b/utils/utils.tcl
@@ -60,6 +60,15 @@ proc pblock_tiles {pblock} {
 	return [get_tiles "$clb_tiles $int_tiles"]
 }
 
+proc lintersect {lst1 lst2} {
+	set rlst {}
+	foreach el $lst1 {
+		set idx [lsearch $lst2 $el]
+		if {$idx >= 0} {lappend rlst $el}
+	}
+	return $rlst
+}
+
 proc putl {lst} {
 	foreach line $lst {puts $line}
 }