diff --git a/fuzzers/001-part-yaml/generate.tcl b/fuzzers/001-part-yaml/generate.tcl
index f95d3e2d..6a9b3ed8 100644
--- a/fuzzers/001-part-yaml/generate.tcl
+++ b/fuzzers/001-part-yaml/generate.tcl
@@ -10,6 +10,7 @@ set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_po
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/005-tilegrid/generate.py b/fuzzers/005-tilegrid/generate.py
index 298515fc..1c4fe149 100644
--- a/fuzzers/005-tilegrid/generate.py
+++ b/fuzzers/005-tilegrid/generate.py
@@ -109,7 +109,7 @@ for tile_name, tile_data in database["tiles"].items():
             database["segments"][segment_name] = dict()
             database["segments"][segment_name]["type"] = segtype
             database["segments"][segment_name]["frames"] = 28
-            database["segments"][segment_name]["words"] = 1
+            database["segments"][segment_name]["words"] = 2
 
             if k == 0:
                 database["segments"][segment_name]["tiles"] = [tile_name, interface_tile_name, int_tile_name]
@@ -158,7 +158,7 @@ for segment_name in database["segments"].keys():
         if "baseaddr" in database["segments"][seg]:
             assert database["segments"][seg]["baseaddr"] == [framebase, wordbase]
         else:
-            database["segments"][seg]["baseaddr"] = (framebase, wordbase)
+            database["segments"][seg]["baseaddr"] = [framebase, wordbase]
 
 
 #######################################
diff --git a/fuzzers/005-tilegrid/generate.tcl b/fuzzers/005-tilegrid/generate.tcl
index 5021587a..d1bb7df2 100644
--- a/fuzzers/005-tilegrid/generate.tcl
+++ b/fuzzers/005-tilegrid/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/010-lutinit/generate.tcl b/fuzzers/010-lutinit/generate.tcl
index a358489b..8c5490b5 100644
--- a/fuzzers/010-lutinit/generate.tcl
+++ b/fuzzers/010-lutinit/generate.tcl
@@ -18,6 +18,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/011-ffconfig/generate.tcl b/fuzzers/011-ffconfig/generate.tcl
index cd4efe0e..833b860f 100644
--- a/fuzzers/011-ffconfig/generate.tcl
+++ b/fuzzers/011-ffconfig/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/012-clbn5ffmux/generate.tcl b/fuzzers/012-clbn5ffmux/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/012-clbn5ffmux/generate.tcl
+++ b/fuzzers/012-clbn5ffmux/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/013-clbncy0/generate.tcl b/fuzzers/013-clbncy0/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/013-clbncy0/generate.tcl
+++ b/fuzzers/013-clbncy0/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/014-ffsrcemux/generate.tcl b/fuzzers/014-ffsrcemux/generate.tcl
index 50983877..329580ee 100644
--- a/fuzzers/014-ffsrcemux/generate.tcl
+++ b/fuzzers/014-ffsrcemux/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/015-clbnffmux/generate.tcl b/fuzzers/015-clbnffmux/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/015-clbnffmux/generate.tcl
+++ b/fuzzers/015-clbnffmux/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/016-clbnoutmux/generate.tcl b/fuzzers/016-clbnoutmux/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/016-clbnoutmux/generate.tcl
+++ b/fuzzers/016-clbnoutmux/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/017-clbprecyinit/generate.tcl b/fuzzers/017-clbprecyinit/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/017-clbprecyinit/generate.tcl
+++ b/fuzzers/017-clbprecyinit/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/018-clbram/generate.tcl b/fuzzers/018-clbram/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/018-clbram/generate.tcl
+++ b/fuzzers/018-clbram/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/019-ndi1mux/generate.tcl b/fuzzers/019-ndi1mux/generate.tcl
index 86162f92..9e981032 100644
--- a/fuzzers/019-ndi1mux/generate.tcl
+++ b/fuzzers/019-ndi1mux/generate.tcl
@@ -15,6 +15,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
diff --git a/fuzzers/050-intpips/README b/fuzzers/050-intpips/README
deleted file mode 100644
index fd64df07..00000000
--- a/fuzzers/050-intpips/README
+++ /dev/null
@@ -1,6 +0,0 @@
-
-Experiment looking into the INT PIPs
-====================================
-
-Results: ???
-
diff --git a/fuzzers/050-intpips/README.md b/fuzzers/050-intpips/README.md
new file mode 100644
index 00000000..3c59b925
--- /dev/null
+++ b/fuzzers/050-intpips/README.md
@@ -0,0 +1,7 @@
+
+Generic fuzzer for INT PIPs
+---------------------------
+
+Run this fuzzer a few times until it stops adding new PIPs to the
+database.
+
diff --git a/fuzzers/051-imuxlout/README.md b/fuzzers/051-imuxlout/README.md
new file mode 100644
index 00000000..d60a1f8d
--- /dev/null
+++ b/fuzzers/051-imuxlout/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for INT LOGIC\_OUTS -> IMUX PIPs
+---------------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/051-imuxlout/generate.tcl b/fuzzers/051-imuxlout/generate.tcl
index 9e0ea29c..ec5255f1 100644
--- a/fuzzers/051-imuxlout/generate.tcl
+++ b/fuzzers/051-imuxlout/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/052-clkin/README.md b/fuzzers/052-clkin/README.md
new file mode 100644
index 00000000..e7620d1e
--- /dev/null
+++ b/fuzzers/052-clkin/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for INT PIPs driving the CLK wires
+-----------------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/052-clkin/generate.py b/fuzzers/052-clkin/generate.py
index 01234d8d..53f43ad6 100644
--- a/fuzzers/052-clkin/generate.py
+++ b/fuzzers/052-clkin/generate.py
@@ -59,7 +59,7 @@ for tile, pips_srcs_dsts in tiledata.items():
             segmk.addtag(tile, "%s.%s" % (dst, src), 0)
 
 def bitfilter(frame_idx, bit_idx):
-    assert os.getenv("XRAY_DATABASE") == "artix7"
+    assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
     if frame_idx == 0 and bit_idx == 48:
         return False
     if frame_idx == 1 and bit_idx == 31:
diff --git a/fuzzers/052-clkin/generate.tcl b/fuzzers/052-clkin/generate.tcl
index 6e76bd36..d4aaa065 100644
--- a/fuzzers/052-clkin/generate.tcl
+++ b/fuzzers/052-clkin/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/053-ctrlin/README.md b/fuzzers/053-ctrlin/README.md
new file mode 100644
index 00000000..b0491f8e
--- /dev/null
+++ b/fuzzers/053-ctrlin/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for INT PIPs driving the CTRL wires
+------------------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/053-ctrlin/generate.py b/fuzzers/053-ctrlin/generate.py
index 23ead416..cb934dcb 100644
--- a/fuzzers/053-ctrlin/generate.py
+++ b/fuzzers/053-ctrlin/generate.py
@@ -59,7 +59,7 @@ for tile, pips_srcs_dsts in tiledata.items():
             segmk.addtag(tile, "%s.%s" % (dst, src), 0)
 
 def bitfilter(frame_idx, bit_idx):
-    assert os.getenv("XRAY_DATABASE") == "artix7"
+    assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
     if (frame_idx, bit_idx) in [(0, 48), (1, 31), (0, 32), (1, 35)]:
         return False
     return frame_idx in [0, 1]
diff --git a/fuzzers/053-ctrlin/generate.tcl b/fuzzers/053-ctrlin/generate.tcl
index 6bdaf747..75301594 100644
--- a/fuzzers/053-ctrlin/generate.tcl
+++ b/fuzzers/053-ctrlin/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/054-gfan/README.md b/fuzzers/054-gfan/README.md
new file mode 100644
index 00000000..759b168f
--- /dev/null
+++ b/fuzzers/054-gfan/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for INT PIPs driving the GFAN wires
+------------------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/054-gfan/generate.tcl b/fuzzers/054-gfan/generate.tcl
index b8fb9d1e..71d7e8a8 100644
--- a/fuzzers/054-gfan/generate.tcl
+++ b/fuzzers/054-gfan/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/055-gnd/README.md b/fuzzers/055-gnd/README.md
new file mode 100644
index 00000000..2ddb1f56
--- /dev/null
+++ b/fuzzers/055-gnd/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for INT PIPs driving the GFAN wires with GND
+---------------------------------------------------
+
+Run this fuzzer once.
+
diff --git a/fuzzers/055-gnd/generate.tcl b/fuzzers/055-gnd/generate.tcl
index 454e722b..aabb6ee0 100644
--- a/fuzzers/055-gnd/generate.tcl
+++ b/fuzzers/055-gnd/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/056-rempips/README.md b/fuzzers/056-rempips/README.md
new file mode 100644
index 00000000..71d44531
--- /dev/null
+++ b/fuzzers/056-rempips/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for the remaining INT PIPs
+---------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/056-rempips/generate.tcl b/fuzzers/056-rempips/generate.tcl
index dbe686a8..5f160173 100644
--- a/fuzzers/056-rempips/generate.tcl
+++ b/fuzzers/056-rempips/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/057-bipips/README.md b/fuzzers/057-bipips/README.md
new file mode 100644
index 00000000..ff0d6008
--- /dev/null
+++ b/fuzzers/057-bipips/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for bidirectional INT PIPs
+---------------------------------
+
+Run this fuzzer a few times until it produces an empty todo.txt file.
+
diff --git a/fuzzers/057-bipips/generate.py b/fuzzers/057-bipips/generate.py
index c334bc06..8c2810fa 100644
--- a/fuzzers/057-bipips/generate.py
+++ b/fuzzers/057-bipips/generate.py
@@ -41,7 +41,7 @@ for tile, pips_nodes in tiledata.items():
             segmk.addtag(tile, "%s.%s" % (dst, src), 0)
 
 def bitfilter(frame_idx, bit_idx):
-    assert os.getenv("XRAY_DATABASE") == "artix7"
+    assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
     return frame_idx in [0, 1]
 
 segmk.compile(bitfilter=bitfilter)
diff --git a/fuzzers/057-bipips/generate.tcl b/fuzzers/057-bipips/generate.tcl
index c2d572b8..bc07c66a 100644
--- a/fuzzers/057-bipips/generate.tcl
+++ b/fuzzers/057-bipips/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/058-hclkpips/README.md b/fuzzers/058-hclkpips/README.md
new file mode 100644
index 00000000..d40cb638
--- /dev/null
+++ b/fuzzers/058-hclkpips/README.md
@@ -0,0 +1,6 @@
+
+Fuzzer for PIPs in HCLK titles
+------------------------------
+
+Run this fuzzer once.
+
diff --git a/fuzzers/058-hclkpips/generate.tcl b/fuzzers/058-hclkpips/generate.tcl
index 337c5f1e..0737adca 100644
--- a/fuzzers/058-hclkpips/generate.tcl
+++ b/fuzzers/058-hclkpips/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/070-tileconn/generate.tcl b/fuzzers/070-tileconn/generate.tcl
index 659bbdd7..06d841c0 100644
--- a/fuzzers/070-tileconn/generate.tcl
+++ b/fuzzers/070-tileconn/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl
index c47709c2..b896ed6b 100644
--- a/fuzzers/071-ppips/generate.tcl
+++ b/fuzzers/071-ppips/generate.tcl
@@ -12,6 +12,7 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_param tcl.collectionResultDisplayLimit 0
 
 place_design
 route_design
diff --git a/htmlgen/htmlgen.py b/htmlgen/htmlgen.py
index 010bb6ef..afafc9ad 100755
--- a/htmlgen/htmlgen.py
+++ b/htmlgen/htmlgen.py
@@ -164,6 +164,8 @@ for segname, segdata in grid["segments"].items():
     segtype = segdata["type"].lower()
 
     if segtype not in segbits:
+        print("Loading data for %s segments:" % segtype)
+
         segbits[segtype] = dict()
         segbits_r[segtype] = dict()
         routebits[segtype] = dict()
@@ -194,7 +196,7 @@ for segname, segdata in grid["segments"].items():
             segbits_r[segtype][bit_pos] = bit_name
 
         if segtype not in ["hclk_l", "hclk_r"]:
-            print("Loading %s segbits." % segtype)
+            print("  loading %s segbits." % segtype)
             with db_open("segbits_%s.db" % segtype) as f:
                 for line in f:
                     if re.search(r"(\.[ABCD]MUX\.)|(\.PRECYINIT\.)", line):
@@ -202,15 +204,17 @@ for segname, segdata in grid["segments"].items():
                     else:
                         add_single_bit(line)
 
-        print("Loading %s segbits." % re.sub("clbl[lm]", "int", segtype))
-        with db_open("segbits_%s.db" % re.sub("clbl[lm]", "int", segtype)) as f:
+        int_tile_type = re.sub("clbl[lm]|bram[0-4]|dsp[0-4]", "int", segtype)
+
+        print("  loading %s segbits." % int_tile_type)
+        with db_open("segbits_%s.db" % int_tile_type) as f:
             for line in f:
                 if segtype in ["hclk_l", "hclk_r"] and ".ENABLE_BUFFER." in line:
                     add_single_bit(line)
                 else:
                     add_pip_bits(line)
 
-        print("Loading %s maskbits." % segtype)
+        print("  loading %s maskbits." % segtype)
         with db_open("mask_%s.db" % segtype) as f:
             for line in f:
                 _, bit = line.split()
@@ -310,7 +314,7 @@ for segtype in sorted(segbits.keys()):
             print("<h3>X-Ray %s Database: %s Segment</h3>" % (get_setting("XRAY_DATABASE").upper(), segtype.upper()), file=f)
         else:
             print("<h3>X-Ray %s Database: %s Segment (%s Tile + %s Tile)</h3>" % (get_setting("XRAY_DATABASE").upper(), segtype.upper(),
-                    segtype.upper(), re.sub("clbl[lm]", "int", segtype).upper()), file=f)
+                    segtype.upper(), re.sub("clbl[lm]|bram[0-4]|dsp[0-4]", "int", segtype).upper()), file=f)
 
         print("""
 <script><!--
diff --git a/utils/dbfixup.py b/utils/dbfixup.py
index f7840bf9..87be71a2 100644
--- a/utils/dbfixup.py
+++ b/utils/dbfixup.py
@@ -88,15 +88,13 @@ def update_mask(mask_db, *src_dbs):
     bits = set()
     mask_db_file = "%s/%s/mask_%s.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"), mask_db)
 
-    if not os.path.exists(mask_db_file):
-        return
-
-    with open(mask_db_file, "r") as f:
-        for line in f:
-            line = line.split()
-            assert len(line) == 2
-            assert line[0] == "bit"
-            bits.add(line[1])
+    if os.path.exists(mask_db_file):
+        with open(mask_db_file, "r") as f:
+            for line in f:
+                line = line.split()
+                assert len(line) == 2
+                assert line[0] == "bit"
+                bits.add(line[1])
 
     for src_db in src_dbs:
         seg_db_file = "%s/%s/segbits_%s.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"), src_db)
@@ -111,9 +109,10 @@ def update_mask(mask_db, *src_dbs):
                     if bit[0] != "!":
                         bits.add(bit)
 
-    with open(mask_db_file, "w") as f:
-        for bit in sorted(bits):
-            print("bit %s" % bit, file=f)
+    if len(bits) > 0:
+        with open(mask_db_file, "w") as f:
+            for bit in sorted(bits):
+                print("bit %s" % bit, file=f)
 
 add_zero_bits("int_l")
 add_zero_bits("int_r")
@@ -129,3 +128,9 @@ update_mask("clblm_r", "clblm_r", "int_r")
 update_mask("hclk_l", "hclk_l")
 update_mask("hclk_r", "hclk_r")
 
+for k in range(5):
+    update_mask("bram%d_l" % k, "bram%d_l" % k, "int_l")
+    update_mask("bram%d_r" % k, "bram%d_r" % k, "int_r")
+    update_mask("dsp%d_l" % k, "dsp%d_l" % k, "int_l")
+    update_mask("dsp%d_r" % k, "dsp%d_r" % k, "int_r")
+