From 0cc1695f3b2aa08961571bf52b5fa4395cb18b37 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Mon, 9 Apr 2018 13:08:46 +1000 Subject: [PATCH 1/5] Merged glossary from prjxray wiki and tidied up some terms. Signed-off-by: Sarah Maddox --- docs/architecture/glossary.rst | 120 +++++++++++++++++++++++++-------- 1 file changed, 91 insertions(+), 29 deletions(-) diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst index ef29cec2..dec0ece5 100644 --- a/docs/architecture/glossary.rst +++ b/docs/architecture/glossary.rst @@ -3,70 +3,132 @@ Glossary .. glossary:: - basic element BEL - basic logic element BLE - For example a LUT5, LUT6, CARRY4, or MUX, but not PIPs. + Basic element (BEL) or basic logic element (BLE) + BELs or BLEs are the basic logic elements in an FPGA, including + carry or fast adders (CFAs), flip flops (FFs), lookup tables (LUTs), + multiplexers (MUXes), and other element types. + Note: Programmable interconnects (PIPs) are not counted as BELs. - BELs come in two types: + BELs come in two forms: * Basic BEL - A logic unit which does things. - * Routing BEL - A unit which is statically configured at the routing time. + * Routing BEL - A unit which is statically configured at routing time. - bitstream + Bitstream Binary data that is directly loaded into an FPGA to perform configuration. Contains configuration :term:`frames ` as well as programming sequences and other commands required to load and activate same. - clock domain + Clock domain Portion of a :term:`horizontal clock row` to one side of the global clock spine. Often refers to :term:`tiles ` that are associated with these clocks. - column - Collection of :term:`tiles ` physically organized as a vertical line. + Column + A term used in :term:`bitstream` configuration to denote + a collection of :term:`tiles `, physically organized as + a vertical line, and configured by the same set of configuration frames. + Logic columns span 50 tiles vertically and 2 tiles horizontally + (pairs of logic tiles and interconnect tiles). - configurable logic block CLB - Basic building block of logic. + Configurable logic block (CLB) + The configurable logic unit of an FPGA. Also called a **logic cell**. + A CLB is a combination of basic logic elements (:term:`BELs `). - frame - Fundamental unit of configuration data consisting of 101 :term:`words `. + Database + A term used in *Project X-Ray* to denote + text files containing meaningful labels for bit positions within + :term:`segments `. - half + Frame + The fundamental unit of :term:`bitstream` configuration data consisting of + 101 :term:`words `. + Each frame has a 32-bit frame address and 101 payload words, 32 bits each. + The 50th payload words is an EEC. + The 7 LSB bits of the frame address are the frame index within the + configuration :term:`column` (called *minor frame address* in the Xilinx + documentation). The rest of the frame address identifies the configuration + column (called *base frame address* in Project X-Ray nomenclature). + + The bits in an individual frame are spread out over the entire column. + For example, in a logic column with 50 tiles, the first tile is configured + with the first two words in each frame, the next tile with the next two + words, and so on. + + Frame base address + The first configuration frame address for a :term:`column`. A frame base + address has always the 7 LSB bits cleared. + + Fuzzer + Scripts and a makefile to generate one or more :term:`specimens ` + and then convert the data from those specimens into a :term:`database`. + + Half Portion of a device defined by a virtual line dividing the two sets of global - clock buffers present in a device. The two halves are simply referred to as + clock buffers present in a device. The two halves are referred to as the top and bottom halves. - node - Collection of :term:`wires ` spanning one or more tiles. + Node + A routing node on the device. A node is a collection of :term:`wires ` + spanning one or more "tiles"term" `tiles `. + Nodes that are local to a tile map 1:1 to a wire. A node that spans multiple + tiles maps to multiple wires, one in each tile it spans. - programmable interconnect point PIP + Programmable interconnect point (PIP) Connection point between two wires in a tile that may be enabled or disabled by the configuration. - horizontal clock row + Horizontal clock row Portion of a device including 12 horizontal clocks and the 50 interconnect and function tiles associated with them. A :term:`half` contains one or more horizontal clock rows and each half may have a different number of rows. + + ROI + Region of interest (ROI) + A term used in *Project X-Ray* to denote a + rectangular region on the FPGA that is the current focus of our study. + Right now this is `SLICE_X12Y100:SLICE_X27Y149` on a `xc7a50tfgg484-1` + chip. - site - Portion of a tile where :term:`BELs ` can be placed. :term:`Slices - ` in a :term:`CLB` tile are sites. + Segment + All configuration bits for a horizontal slice of a :term:`column`. + This corresponds to two ranges: a range of :term:`frames ` + and a range of :term:`words ` within frames. A segment of a logic + column is 36 frames wide and 2 words high. - slice - Portion of a :term:`CLB` tile that contains :term:`BELs `. + Site + Portion of a tile where :term:`BELs ` can be placed. The + :term:`slices ` in a :term:`CLB` tile are sites. - tile + Slice + Portion of a :term:`tile` tile that contains :term:`BELs `. + A `CLBLL_L/CLBLL_R` tile contains two `SLICEL` slices. + A `CLBLM_L/CLBLM_R` tile contains one `SLICEL` slice and one `SLICEM` slice. + + Specimen + A :term:`bitstream` of a (usually auto-generated) design with additional + files containing information about the placed and routed design. + These additional files are usually generated using Vivado TCL scripts + querying the Vivado design database. + + Tile Fundamental unit of physical structure containing a single type of - resource or function. + resource or function. A container for :term:`sites ` and + :term:`slices `. The whole chip is a grid of tiles. - wire + The most important tile types are left and right interconnect tiles + (`INT_L` and `INT_R`) and left and right :term:`CLB` logic/memory tiles + (`CLBLL_L`, `CLBLL_R`, `CLBLM_L`, `CLBLM_R`). + + Wire Physical wire within a :term:`tile`. - word - 32-bits stored in big-endian order. Fundamental unit of :term:`bitstream` format. + Word + 32 bits stored in big-endian order. Fundamental unit of :term:`bitstream` + format. From cdf9ba9135fafff4e1ba48f154f64ebbc2b92955 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Mon, 16 Apr 2018 10:48:41 +1000 Subject: [PATCH 2/5] Fixed some RST errors. Signed-off-by: Sarah Maddox --- docs/architecture/glossary.rst | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst index dec0ece5..b392c9f9 100644 --- a/docs/architecture/glossary.rst +++ b/docs/architecture/glossary.rst @@ -40,15 +40,14 @@ Glossary A CLB is a combination of basic logic elements (:term:`BELs `). Database - A term used in *Project X-Ray* to denote - text files containing meaningful labels for bit positions within + Text files containing meaningful labels for bit positions within :term:`segments `. Frame The fundamental unit of :term:`bitstream` configuration data consisting of 101 :term:`words `. Each frame has a 32-bit frame address and 101 payload words, 32 bits each. - The 50th payload words is an EEC. + The 50th payload word is an EEC. The 7 LSB bits of the frame address are the frame index within the configuration :term:`column` (called *minor frame address* in the Xilinx documentation). The rest of the frame address identifies the configuration @@ -74,7 +73,7 @@ Glossary Node A routing node on the device. A node is a collection of :term:`wires ` - spanning one or more "tiles"term" `tiles `. + spanning one or more :term:`tiles `. Nodes that are local to a tile map 1:1 to a wire. A node that spans multiple tiles maps to multiple wires, one in each tile it spans. @@ -93,8 +92,8 @@ Glossary Region of interest (ROI) A term used in *Project X-Ray* to denote a rectangular region on the FPGA that is the current focus of our study. - Right now this is `SLICE_X12Y100:SLICE_X27Y149` on a `xc7a50tfgg484-1` - chip. + The current region of interest is `SLICE_X12Y100:SLICE_X27Y149` + on a `xc7a50tfgg484-1` chip. Segment All configuration bits for a horizontal slice of a :term:`column`. @@ -107,7 +106,7 @@ Glossary :term:`slices ` in a :term:`CLB` tile are sites. Slice - Portion of a :term:`tile` tile that contains :term:`BELs `. + Portion of a :term:`tile` that contains :term:`BELs `. A `CLBLL_L/CLBLL_R` tile contains two `SLICEL` slices. A `CLBLM_L/CLBLM_R` tile contains one `SLICEL` slice and one `SLICEM` slice. From 696d1c4140c887d1b5ea32d1b5b3c835fcab67f9 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Wed, 18 Apr 2018 14:21:43 +1000 Subject: [PATCH 3/5] Added separate lines for BLE long-form definitions. Signed-off-by: Sarah Maddox --- docs/architecture/glossary.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst index b392c9f9..de18fd9b 100644 --- a/docs/architecture/glossary.rst +++ b/docs/architecture/glossary.rst @@ -3,10 +3,12 @@ Glossary .. glossary:: + basic element BEL + basic logic element BLE - Basic element (BEL) or basic logic element (BLE) - BELs or BLEs are the basic logic elements in an FPGA, including + Basic elements (BELs) or basic logic element (BLEs) + are the basic logic units in an FPGA, including carry or fast adders (CFAs), flip flops (FFs), lookup tables (LUTs), multiplexers (MUXes), and other element types. Note: Programmable interconnects (PIPs) are not counted as BELs. From 59082d953048b78d58840b7608961668c831da50 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Wed, 18 Apr 2018 15:18:43 +1000 Subject: [PATCH 4/5] Fixes link to non-existent glossary entry. Signed-off-by: Sarah Maddox --- docs/architecture/overview.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/architecture/overview.rst b/docs/architecture/overview.rst index ec66cfb1..4e1a139a 100644 --- a/docs/architecture/overview.rst +++ b/docs/architecture/overview.rst @@ -28,6 +28,6 @@ may be used within a single clock domain, connected to span both clock domains in a horizontal clock row, or connected to global clocks. Clock domains have a fixed height of 50 :term:`interconnect tiles -` centered around the horizontal clock lines (25 above, 25 +` centered around the horizontal clock lines (25 above, 25 below). Various function tiles, such as :term:`CLBs `, are attached to interconnect tiles. From e962ca40da9abd724a5e146c2762dada248502d6 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Thu, 19 Apr 2018 11:59:22 +1000 Subject: [PATCH 5/5] Modified some terms that include abbreviations and fixed alphabetical order. Signed-off-by: Sarah Maddox --- docs/architecture/glossary.rst | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst index de18fd9b..5687022a 100644 --- a/docs/architecture/glossary.rst +++ b/docs/architecture/glossary.rst @@ -37,9 +37,10 @@ Glossary (pairs of logic tiles and interconnect tiles). CLB - Configurable logic block (CLB) - The configurable logic unit of an FPGA. Also called a **logic cell**. - A CLB is a combination of basic logic elements (:term:`BELs `). + Configurable logic block + A configurable logic block (CLB) is the configurable logic unit of an FPGA. + Also called a **logic cell**. A CLB is a combination of basic logic elements + (:term:`BELs `). Database Text files containing meaningful labels for bit positions within @@ -73,6 +74,12 @@ Glossary clock buffers present in a device. The two halves are referred to as the top and bottom halves. + Horizontal clock row + Portion of a device including 12 horizontal clocks and the 50 interconnect + and function tiles associated with them. A :term:`half` contains one or + more horizontal clock rows and each half may have a different number of + rows. + Node A routing node on the device. A node is a collection of :term:`wires ` spanning one or more :term:`tiles `. @@ -80,19 +87,13 @@ Glossary tiles maps to multiple wires, one in each tile it spans. PIP - Programmable interconnect point (PIP) - Connection point between two wires in a tile that may be enabled or - disabled by the configuration. - - Horizontal clock row - Portion of a device including 12 horizontal clocks and the 50 interconnect - and function tiles associated with them. A :term:`half` contains one or - more horizontal clock rows and each half may have a different number of - rows. + Programmable interconnect point + A programmable interconnect point (PIP) is a connection point between two + wires in a tile that may be enabled or disabled by the configuration. ROI - Region of interest (ROI) - A term used in *Project X-Ray* to denote a + Region of interest + Region of interest (ROI) is used in *Project X-Ray* to denote a rectangular region on the FPGA that is the current focus of our study. The current region of interest is `SLICE_X12Y100:SLICE_X27Y149` on a `xc7a50tfgg484-1` chip.