diff --git a/.github/kokoro/ctest2junit.xsl b/.github/kokoro/ctest2junit.xsl index 3ea29e50..8ba21f4e 100644 --- a/.github/kokoro/ctest2junit.xsl +++ b/.github/kokoro/ctest2junit.xsl @@ -1,120 +1,120 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BuildName: - BuildStamp: - Name: - Generator: - CompilerName: - OSName: - Hostname: - OSRelease: - OSVersion: - OSPlatform: - Is64Bits: - VendorString: - VendorID: - FamilyID: - ModelID: - ProcessorCacheSize: - NumberOfLogicalCPU: - NumberOfPhysicalCPU: - TotalVirtualMemory: - TotalPhysicalMemory: - LogicalProcessorsPerPhysical: - ProcessorClockFrequency: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + BuildName: + BuildStamp: + Name: + Generator: + CompilerName: + OSName: + Hostname: + OSRelease: + OSVersion: + OSPlatform: + Is64Bits: + VendorString: + VendorID: + FamilyID: + ModelID: + ProcessorCacheSize: + NumberOfLogicalCPU: + NumberOfPhysicalCPU: + TotalVirtualMemory: + TotalPhysicalMemory: + LogicalProcessorsPerPhysical: + ProcessorClockFrequency: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Makefile b/Makefile index d8f35aab..03cae068 100644 --- a/Makefile +++ b/Makefile @@ -58,7 +58,7 @@ test-cpp: # Auto formatting of code. # ------------------------ -FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*') +FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*') -and -not -name *.bit CLANG_FORMAT ?= clang-format-5.0 format-cpp: @@ -76,10 +76,34 @@ TCL_FORMAT ?= utils//tcl-reformat.sh format-tcl: find . -name \*.tcl $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) -n 1 $(TCL_FORMAT) -format: format-cpp format-docs format-py format-tcl +# Command to find and replace trailing whitespace in-place using `sed` (This is +# placed inside quotes later so need to escape the "'") +WS_CMD = sed -i '\''s@\s\+$$@@g'\'' + +# File filter for files to fix trailing whitespace in, this is just a couple of +# chained bash conditionals ensuring that the file (indicated by {}, provided by +# xargs later) is a file, and not a directory or link. Also filters out .bit +# files as these are the only binary files currently tracked by Git and we don't +# want to inadvertently change these at all. +WS_FILTER = [ -f {} -a ! -L {} ] && [[ {} != *.bit ]] + +# For every file piped to $(WS_FORMAT) apply the filter and perform the command, +# if a file does not match the filter, just returns true. +WS_FORMAT = xargs -P $$(nproc) -n 1 -I{} bash -c '$(WS_FILTER) && $(WS_CMD) {} || true' + +format-trailing-ws: + # Use `git ls-files` to give us a complete list of tracked files to fix + # whitespace in; there is no point spending time processing anything that is + # not known to Git. + git ls-files | $(WS_FORMAT) + + # Additionally fix untracked (but not ignored) files. + git ls-files -o --exclude-standard | $(WS_FORMAT) + +format: format-cpp format-docs format-py format-tcl format-trailing-ws @true -.PHONY: format format-cpp format-py format-tcl +.PHONY: format format-cpp format-py format-tcl format-trailing-ws # Targets related to Project X-Ray databases # ------------------------ diff --git a/fuzzers/011-clb-ffconfig/README.md b/fuzzers/011-clb-ffconfig/README.md index e58b766e..b2a0178e 100644 --- a/fuzzers/011-clb-ffconfig/README.md +++ b/fuzzers/011-clb-ffconfig/README.md @@ -34,7 +34,7 @@ Configures whether a storage element is synchronous or asynchronous. Scope: entire site (not individual FFs) -| FFSYNC | Reset | Applicable prims | +| FFSYNC | Reset | Applicable prims | |--------|--------------|---------------------------| |0 | Synchronous | FDPE, FDCE, LDCE, LDPE | |1 | Asynchronous | FDSE, FDRE | diff --git a/fuzzers/011-clb-ffconfig/generate.py b/fuzzers/011-clb-ffconfig/generate.py index 9f740481..7cb03d0e 100644 --- a/fuzzers/011-clb-ffconfig/generate.py +++ b/fuzzers/011-clb-ffconfig/generate.py @@ -58,7 +58,7 @@ with open("design.txt", "r") as f: puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr" CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE - CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0 + CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0 ''' line = line.split() tile_type = line[0] diff --git a/fuzzers/013-clb-ncy0/minitest/top.v b/fuzzers/013-clb-ncy0/minitest/top.v index 712094c6..67d14cd5 100644 --- a/fuzzers/013-clb-ncy0/minitest/top.v +++ b/fuzzers/013-clb-ncy0/minitest/top.v @@ -94,7 +94,7 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout); always @(*) begin s = din[7:4]; s[N] = o6; - + di = {din[3:0]}; di[N] = o5; end diff --git a/fuzzers/015-clb-nffmux/top.py b/fuzzers/015-clb-nffmux/top.py index 8cc79b72..776baf41 100644 --- a/fuzzers/015-clb-nffmux/top.py +++ b/fuzzers/015-clb-nffmux/top.py @@ -143,7 +143,7 @@ module myLUT8 (input clk, input [7:0] din, .O6(lutno6[1])); generate if (ALUT_SRL != 0) begin - + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) SRLC32E #( .INIT(64'h8000_1CE0_0000_0001) @@ -158,7 +158,7 @@ module myLUT8 (input clk, input [7:0] din, assign lutno5[0] = din[6]; end else begin - + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) LUT6_2 #( .INIT(64'h8000_1CE0_0000_0001) diff --git a/fuzzers/016-clb-noutmux/minitest/top.v b/fuzzers/016-clb-noutmux/minitest/top.v index 2081709a..eb4c4d4a 100644 --- a/fuzzers/016-clb-noutmux/minitest/top.v +++ b/fuzzers/016-clb-noutmux/minitest/top.v @@ -51,7 +51,7 @@ module roi(input clk, input [255:0] din, output [255:0] dout); clb_NOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ])); //ok clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N)) - clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ])); + clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ])); endmodule module myLUT8 (input clk, input [7:0] din, diff --git a/fuzzers/016-clb-noutmux/top.py b/fuzzers/016-clb-noutmux/top.py index 2d513066..dd559554 100644 --- a/fuzzers/016-clb-noutmux/top.py +++ b/fuzzers/016-clb-noutmux/top.py @@ -147,7 +147,7 @@ module myLUT8 (input clk, input [7:0] din, .O6(lutno6[1])); generate if (ALUT_SRL != 0) begin - + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) SRLC32E #( .INIT(64'h8000_1CE0_0000_0001) @@ -162,7 +162,7 @@ module myLUT8 (input clk, input [7:0] din, assign lutno5[0] = din[6]; end else begin - + (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *) LUT6_2 #( .INIT(64'h8000_1CE0_0000_0001) diff --git a/fuzzers/018-clb-ram/minitest/README.md b/fuzzers/018-clb-ram/minitest/README.md index b5bb9b7f..00e0e951 100644 --- a/fuzzers/018-clb-ram/minitest/README.md +++ b/fuzzers/018-clb-ram/minitest/README.md @@ -1,12 +1,12 @@ # CLB_RAM Minitest ## Purpose -SLICEM RAM test -LUT6 => 64 bits -Focus on 64 bit -32 probably uses same O5/O6 stuff -128 probably uses same MUX stuff -Why isn't there a 256? +SLICEM RAM test +LUT6 => 64 bits +Focus on 64 bit +32 probably uses same O5/O6 stuff +128 probably uses same MUX stuff +Why isn't there a 256? ## Result ``` diff --git a/fuzzers/019-clb-ndi1mux/minitest/README.md b/fuzzers/019-clb-ndi1mux/minitest/README.md index 05380824..a7e541ce 100644 --- a/fuzzers/019-clb-ndi1mux/minitest/README.md +++ b/fuzzers/019-clb-ndi1mux/minitest/README.md @@ -1,18 +1,18 @@ # CLB_nDI1MUX Minitest ## Purpose -Trying to set SLICEM LUT DI1 inputs -These exist for LUTA, LUTB, and LUTC only -Can either be an external signal, another LUT's data input, or another LUT's carry -Note: mux input pattern is irregular +Trying to set SLICEM LUT DI1 inputs +These exist for LUTA, LUTB, and LUTC only +Can either be an external signal, another LUT's data input, or another LUT's carry +Note: mux input pattern is irregular ## Result -The following bits are set for NI but not NMC31: +The following bits are set for NI but not NMC31: ``` bit 00_00 ADI1MUX.AI bit 00_20 BDI1MUX.BI bit 01_43 BDI1MUX.CI ``` -Additionally, test with unknown DI mux bits don't appear near NI bits -There is something strange going on +Additionally, test with unknown DI mux bits don't appear near NI bits +There is something strange going on diff --git a/fuzzers/030-iob/minitest/README.md b/fuzzers/030-iob/minitest/README.md index 8dcc2fdb..58566b0d 100644 --- a/fuzzers/030-iob/minitest/README.md +++ b/fuzzers/030-iob/minitest/README.md @@ -22,8 +22,8 @@ DRIVE 38_64 38_66 38_72 38_74 39_65 39_73 LVCMOS25 DRIVE 38_64 38_66 38_72 38_74 39_65 39_73 4 X X X -8 X -12 +8 X +12 16 X X X LVCMOS33 diff --git a/fuzzers/030-iob/minitest/top.v b/fuzzers/030-iob/minitest/top.v index 0e8f32b8..5b7fb484 100644 --- a/fuzzers/030-iob/minitest/top.v +++ b/fuzzers/030-iob/minitest/top.v @@ -145,7 +145,7 @@ endmodule */ /* -ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1 +ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1 ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer hmm Abandoning verilog approach diff --git a/fuzzers/059-pip-byp-bounce/README.md b/fuzzers/059-pip-byp-bounce/README.md index 8db61e68..0de34c58 100644 --- a/fuzzers/059-pip-byp-bounce/README.md +++ b/fuzzers/059-pip-byp-bounce/README.md @@ -1,4 +1,4 @@ -Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs +Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs --------------------------------------- This fuzzer solves the FAN_ALT.BYP_BOUNCE PIPs which were occasionally solved incorrectly in 050-pip-seed or 056-pip-rem. diff --git a/fuzzers/074-dump_all/cleanup_site_pins.py b/fuzzers/074-dump_all/cleanup_site_pins.py index 5ae67494..0f4005aa 100644 --- a/fuzzers/074-dump_all/cleanup_site_pins.py +++ b/fuzzers/074-dump_all/cleanup_site_pins.py @@ -51,7 +51,7 @@ def find_origin_coordinate(sites): def create_site_pin_to_wire_maps(tile_name, nodes): """ Create a map from site_pin names to nodes. - Create a mapping from site pins to tile local wires. For each node that is + Create a mapping from site pins to tile local wires. For each node that is attached to a site pin, there should only be 1 tile local wire. """ diff --git a/gridinfo/runme.sh b/gridinfo/runme.sh index 302a3d09..41aa4f32 100755 --- a/gridinfo/runme.sh +++ b/gridinfo/runme.sh @@ -22,12 +22,12 @@ EOT cat > design.v << EOT module top(input [5:0] I, output O); LUT6 #(.INIT(64'h8000000000000000)) lut ( - .I0(I[0]), - .I1(I[1]), - .I2(I[2]), - .I3(I[3]), - .I4(I[4]), - .I5(I[5]), + .I0(I[0]), + .I1(I[1]), + .I2(I[2]), + .I3(I[3]), + .I4(I[4]), + .I5(I[5]), .O(O) ); endmodule diff --git a/lib/segbits_file_reader.cc b/lib/segbits_file_reader.cc index df85fab3..b06b674e 100644 --- a/lib/segbits_file_reader.cc +++ b/lib/segbits_file_reader.cc @@ -23,7 +23,7 @@ SegbitsFileReader::iterator SegbitsFileReader::end() { } SegbitsFileReader::value_type::value_type(const absl::string_view& view) { - size_t separator_start = view.find_first_of(" \t"); + size_t separator_start = view.find_first_of(" \t\n"); if (separator_start == absl::string_view::npos) { tag_ = view; bit_ = absl::string_view(); diff --git a/lib/test_data/one_entry_missing_bit.segbits b/lib/test_data/one_entry_missing_bit.segbits index d1d77fe2..99a8a8e9 100644 --- a/lib/test_data/one_entry_missing_bit.segbits +++ b/lib/test_data/one_entry_missing_bit.segbits @@ -1 +1 @@ -CLBLL_L.SLICEL_X0.A5FF.ZINI +CLBLL_L.SLICEL_X0.A5FF.ZINI diff --git a/minitests/clb-bused/README.md b/minitests/clb-bused/README.md index d1266797..3d80ba09 100644 --- a/minitests/clb-bused/README.md +++ b/minitests/clb-bused/README.md @@ -4,7 +4,7 @@ Tests for BUSED bit ## Result -However got this +However got this ``` seg SEG_CLBLL_R_X13Y101 bit 30_24 diff --git a/minitests/clb-muxf8/README.md b/minitests/clb-muxf8/README.md index bf3dd25a..d963a85a 100644 --- a/minitests/clb-muxf8/README.md +++ b/minitests/clb-muxf8/README.md @@ -1,13 +1,13 @@ # CLB_MUXF8 Minitest ## Purpose -This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior -The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused) +This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior +The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused) ## General notes: -- 2017.2: LUT6_2 works with MUXF8 -- 2017.3: LUT6_2 does not work with MUXF8 -- All: LUT6 works with MUXF8 -- All: MUXF8 (even with MUXF7) can be instantiated unconnected -- 2017.4 seems to behave like 2017.3 +- 2017.2: LUT6_2 works with MUXF8 +- 2017.3: LUT6_2 does not work with MUXF8 +- All: LUT6 works with MUXF8 +- All: MUXF8 (even with MUXF7) can be instantiated unconnected +- 2017.4 seems to behave like 2017.3 diff --git a/minitests/fixedpnr/README.md b/minitests/fixedpnr/README.md index e236526d..f63a3f65 100644 --- a/minitests/fixedpnr/README.md +++ b/minitests/fixedpnr/README.md @@ -3,7 +3,7 @@ ## Purpose ## Result -Preliminary result +Preliminary result | |00_48|30_12|31_03| |----|-----|-----|-----| diff --git a/minitests/fixedpnr/top_fdce_inv.v b/minitests/fixedpnr/top_fdce_inv.v index c77af698..e69d1b30 100644 --- a/minitests/fixedpnr/top_fdce_inv.v +++ b/minitests/fixedpnr/top_fdce_inv.v @@ -3,7 +3,7 @@ module top(input clk, ce, sr, d, output q); /* IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1, ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop. - However, it is used as a regular flop. + However, it is used as a regular flop. cliff didn't have constrained, also got annoyed he is using slightly later version @@ -30,7 +30,7 @@ module top(input clk, ce, sr, d, output q); IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0, ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop. - However, it is used as a regular flop. + However, it is used as a regular flop. ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors. Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' */ diff --git a/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v b/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v index d8fc6e2d..84ad0e67 100644 --- a/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v +++ b/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v @@ -116,15 +116,15 @@ assign ser_rst = ser_rst_sr[0]; // BUFR - generation of CLKDIV localparam DIVIDE = (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 2) ? "2" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 3) ? "3" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 4) ? "4" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 5) ? "5" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 6) ? "6" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 7) ? "7" : - (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 8) ? "8" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 3) ? "3" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 4) ? "4" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 5) ? "5" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 6) ? "6" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 7) ? "7" : + (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 8) ? "8" : - (ISERDES_MODE == "DDR" && ISERDES_WIDTH == 4) ? "2" : - (ISERDES_MODE == "DDR" && ISERDES_WIDTH == 6) ? "3" : + (ISERDES_MODE == "DDR" && ISERDES_WIDTH == 4) ? "2" : + (ISERDES_MODE == "DDR" && ISERDES_WIDTH == 6) ? "3" : (ISERDES_MODE == "DDR" && ISERDES_WIDTH == 8) ? "4" : "BYPASS"; BUFR # ( diff --git a/minitests/iserdes.idelay/src/message_formatter.v b/minitests/iserdes.idelay/src/message_formatter.v index 66b7f4d6..fbffcbf6 100644 --- a/minitests/iserdes.idelay/src/message_formatter.v +++ b/minitests/iserdes.idelay/src/message_formatter.v @@ -58,10 +58,10 @@ always @(posedge CLK) tx_req <= 1'b0; else case (fsm) - FSM_TX_HEX: tx_req <= 1'b1; - FSM_TX_SEP: tx_req <= 1'b1; - FSM_TX_CR: tx_req <= 1'b1; - FSM_TX_LF: tx_req <= 1'b1; + FSM_TX_HEX: tx_req <= 1'b1; + FSM_TX_SEP: tx_req <= 1'b1; + FSM_TX_CR: tx_req <= 1'b1; + FSM_TX_LF: tx_req <= 1'b1; default: tx_req <= 1'b0; @@ -106,7 +106,7 @@ always @(posedge CLK) FSM_IDLE: if (I_STB) fsm <= FSM_TX_HEX; - FSM_TX_HEX: + FSM_TX_HEX: if (tx_rdy && (char_cnt == 0) && (word_cnt == 0)) fsm <= FSM_TX_CR; else if (tx_rdy && (char_cnt == 0)) fsm <= FSM_TX_SEP; @@ -115,7 +115,7 @@ always @(posedge CLK) FSM_TX_SEP: if (tx_rdy) fsm <= FSM_TX_HEX; FSM_TX_CR: if (tx_rdy) fsm <= FSM_TX_LF; FSM_TX_LF: if (tx_rdy) fsm <= FSM_IDLE; - + endcase // ============================================================================ diff --git a/minitests/iserdes.sdr_ddr/basys3_iserdes_sdr_ddr.v b/minitests/iserdes.sdr_ddr/basys3_iserdes_sdr_ddr.v index b4b6708d..2af6182f 100644 --- a/minitests/iserdes.sdr_ddr/basys3_iserdes_sdr_ddr.v +++ b/minitests/iserdes.sdr_ddr/basys3_iserdes_sdr_ddr.v @@ -44,16 +44,16 @@ wire [9:0] error; genvar i; generate for (i=0; i<10; i=i+1) begin - localparam DATA_WIDTH = (i == 0) ? 2 : - (i == 1) ? 3 : - (i == 2) ? 4 : - (i == 3) ? 5 : - (i == 4) ? 6 : - (i == 5) ? 7 : - (i == 6) ? 8 : - (i == 7) ? 4 : - (i == 8) ? 6 : - /*(i == 9) ?*/ 8; + localparam DATA_WIDTH = (i == 0) ? 2 : + (i == 1) ? 3 : + (i == 2) ? 4 : + (i == 3) ? 5 : + (i == 4) ? 6 : + (i == 5) ? 7 : + (i == 6) ? 8 : + (i == 7) ? 4 : + (i == 8) ? 6 : + /*(i == 9) ?*/ 8; localparam DATA_RATE = (i < 7) ? "SDR" : "DDR"; @@ -66,7 +66,7 @@ generate for (i=0; i<10; i=i+1) begin ( .CLK (CLK), .RST (RST), - + .IO_DAT (io[i]), .O_ERROR (error[i]) ); diff --git a/minitests/iserdes.sdr_ddr/src/comparator.v b/minitests/iserdes.sdr_ddr/src/comparator.v index 8e7be49f..711a6f8e 100644 --- a/minitests/iserdes.sdr_ddr/src/comparator.v +++ b/minitests/iserdes.sdr_ddr/src/comparator.v @@ -88,12 +88,12 @@ always @(posedge CLK) count_err <= count_err + 1; else if (o_bitslip) count_err <= 0; - + always @(posedge CLK) if (RST) o_bitslip <= 1'b0; else if (!o_bitslip && (count_err >= ERROR_COUNT)) - o_bitslip <= 1'b1; + o_bitslip <= 1'b1; else if ( o_bitslip) o_bitslip <= 1'b0; diff --git a/minitests/iserdes.sdr_ddr/src/receiver.v b/minitests/iserdes.sdr_ddr/src/receiver.v index 4be96172..ae3562f0 100644 --- a/minitests/iserdes.sdr_ddr/src/receiver.v +++ b/minitests/iserdes.sdr_ddr/src/receiver.v @@ -26,15 +26,15 @@ wire i_rstdiv; // Divider for BUFR localparam DIVIDE = (MODE == "SDR" && WIDTH == 2) ? "2" : - (MODE == "SDR" && WIDTH == 3) ? "3" : - (MODE == "SDR" && WIDTH == 4) ? "4" : - (MODE == "SDR" && WIDTH == 5) ? "5" : - (MODE == "SDR" && WIDTH == 6) ? "6" : - (MODE == "SDR" && WIDTH == 7) ? "7" : - (MODE == "SDR" && WIDTH == 8) ? "8" : + (MODE == "SDR" && WIDTH == 3) ? "3" : + (MODE == "SDR" && WIDTH == 4) ? "4" : + (MODE == "SDR" && WIDTH == 5) ? "5" : + (MODE == "SDR" && WIDTH == 6) ? "6" : + (MODE == "SDR" && WIDTH == 7) ? "7" : + (MODE == "SDR" && WIDTH == 8) ? "8" : - (MODE == "DDR" && WIDTH == 4) ? "2" : - (MODE == "DDR" && WIDTH == 6) ? "3" : + (MODE == "DDR" && WIDTH == 4) ? "2" : + (MODE == "DDR" && WIDTH == 6) ? "3" : (MODE == "DDR" && WIDTH == 8) ? "4" : "BYPASS"; // BUFR BUFR # diff --git a/minitests/litex/src.vivado/VexRiscv_Linux.v b/minitests/litex/src.vivado/VexRiscv_Linux.v index f11cf036..8c29f40c 100644 --- a/minitests/litex/src.vivado/VexRiscv_Linux.v +++ b/minitests/litex/src.vivado/VexRiscv_Linux.v @@ -3188,7 +3188,7 @@ module VexRiscv ( end end - InstructionCache IBusCachedPlugin_cache ( + InstructionCache IBusCachedPlugin_cache ( .io_flush(_zz_239_), .io_cpu_prefetch_isValid(_zz_240_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), @@ -3234,9 +3234,9 @@ module VexRiscv ( .io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_error(iBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); - DataCache dataCache_1_ ( + DataCache dataCache_1_ ( .io_cpu_execute_isValid(_zz_249_), .io_cpu_execute_address(_zz_250_), .io_cpu_execute_args_wr(_zz_251_), @@ -3289,7 +3289,7 @@ module VexRiscv ( .io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_error(dBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); always @(*) begin case(_zz_498_) diff --git a/minitests/litex/src.yosys/VexRiscv_Linux.v b/minitests/litex/src.yosys/VexRiscv_Linux.v index f11cf036..8c29f40c 100644 --- a/minitests/litex/src.yosys/VexRiscv_Linux.v +++ b/minitests/litex/src.yosys/VexRiscv_Linux.v @@ -3188,7 +3188,7 @@ module VexRiscv ( end end - InstructionCache IBusCachedPlugin_cache ( + InstructionCache IBusCachedPlugin_cache ( .io_flush(_zz_239_), .io_cpu_prefetch_isValid(_zz_240_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), @@ -3234,9 +3234,9 @@ module VexRiscv ( .io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_error(iBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); - DataCache dataCache_1_ ( + DataCache dataCache_1_ ( .io_cpu_execute_isValid(_zz_249_), .io_cpu_execute_address(_zz_250_), .io_cpu_execute_args_wr(_zz_251_), @@ -3289,7 +3289,7 @@ module VexRiscv ( .io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_error(dBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); always @(*) begin case(_zz_498_) diff --git a/minitests/litex/src.yosys/missing_bit_report.py b/minitests/litex/src.yosys/missing_bit_report.py index df5dd9f6..4d4ec472 100644 --- a/minitests/litex/src.yosys/missing_bit_report.py +++ b/minitests/litex/src.yosys/missing_bit_report.py @@ -1,7 +1,7 @@ """ Generates a missing feature/bit report for LiteX design. This script is fairly fragile, because it depends on the specific observation -that all of the remaining bits appear to either belong to HCLK_IOI or IOI3 +that all of the remaining bits appear to either belong to HCLK_IOI or IOI3 tiles. A more general version of this script could be created, but that was not the point of this script. diff --git a/minitests/oserdes/basys3_oserdes_rates.v b/minitests/oserdes/basys3_oserdes_rates.v index 9e80a379..8fa32671 100644 --- a/minitests/oserdes/basys3_oserdes_rates.v +++ b/minitests/oserdes/basys3_oserdes_rates.v @@ -67,16 +67,16 @@ wire [9:0] error; genvar i; generate for (i=0; i<10; i=i+1) begin - localparam DATA_WIDTH = (i == 0) ? 2 : - (i == 1) ? 3 : - (i == 2) ? 4 : - (i == 3) ? 5 : - (i == 4) ? 6 : - (i == 5) ? 7 : - (i == 6) ? 8 : - (i == 7) ? 4 : - (i == 8) ? 6 : - /*(i == 9) ?*/ 8; + localparam DATA_WIDTH = (i == 0) ? 2 : + (i == 1) ? 3 : + (i == 2) ? 4 : + (i == 3) ? 5 : + (i == 4) ? 6 : + (i == 5) ? 7 : + (i == 6) ? 8 : + (i == 7) ? 4 : + (i == 8) ? 6 : + /*(i == 9) ?*/ 8; localparam DATA_RATE = (i < 7) ? "SDR" : "DDR"; diff --git a/minitests/oserdes/src/oserdes_test.v b/minitests/oserdes/src/oserdes_test.v index fdec3c37..cd0352e5 100644 --- a/minitests/oserdes/src/oserdes_test.v +++ b/minitests/oserdes/src/oserdes_test.v @@ -27,17 +27,17 @@ output wire O_ERROR // ============================================================================ // Generate CLK2 and CLKDIV for OSERDES using BUFRs -localparam CLKDIV_DIVIDE = +localparam CLKDIV_DIVIDE = (DATA_RATE == "SDR" && DATA_WIDTH == 2) ? "2" : - (DATA_RATE == "SDR" && DATA_WIDTH == 3) ? "3" : - (DATA_RATE == "SDR" && DATA_WIDTH == 4) ? "4" : - (DATA_RATE == "SDR" && DATA_WIDTH == 5) ? "5" : - (DATA_RATE == "SDR" && DATA_WIDTH == 6) ? "6" : - (DATA_RATE == "SDR" && DATA_WIDTH == 7) ? "7" : - (DATA_RATE == "SDR" && DATA_WIDTH == 8) ? "8" : + (DATA_RATE == "SDR" && DATA_WIDTH == 3) ? "3" : + (DATA_RATE == "SDR" && DATA_WIDTH == 4) ? "4" : + (DATA_RATE == "SDR" && DATA_WIDTH == 5) ? "5" : + (DATA_RATE == "SDR" && DATA_WIDTH == 6) ? "6" : + (DATA_RATE == "SDR" && DATA_WIDTH == 7) ? "7" : + (DATA_RATE == "SDR" && DATA_WIDTH == 8) ? "8" : - (DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "4" : - (DATA_RATE == "DDR" && DATA_WIDTH == 6) ? "6" : + (DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "4" : + (DATA_RATE == "DDR" && DATA_WIDTH == 6) ? "6" : (DATA_RATE == "DDR" && DATA_WIDTH == 8) ? "8" : "BYPASS"; wire CLKX; @@ -93,7 +93,7 @@ always @(posedge CLKDIV) ser_dat <= lfsr_dat; // ============================================================================ -// OSERDES +// OSERDES // OSERDES reset generator (required for it to work properly!) reg [3:0] ser_rst_sr; diff --git a/minitests/partial_reconfig_flow/Makefile b/minitests/partial_reconfig_flow/Makefile index 54f9014d..8e94cd21 100644 --- a/minitests/partial_reconfig_flow/Makefile +++ b/minitests/partial_reconfig_flow/Makefile @@ -5,7 +5,7 @@ # will generate a bitstream that includes both the harness and the .fasm design # ready for programming to a board. For example, # 'make inv_hand_crafted.bit' will generate a bitstream that includes the -# design from roi_noninv.fasm. +# design from roi_noninv.fasm. %_hand_crafted.bit: %_roi_partial.frm harness.bit ${XRAY_TOOLS_DIR}/xc7patch \ --part_name "${XRAY_PART}" \ diff --git a/minitests/plle2_adv/src/plle2_test.v b/minitests/plle2_adv/src/plle2_test.v index dd73b2eb..f9c2f680 100644 --- a/minitests/plle2_adv/src/plle2_test.v +++ b/minitests/plle2_adv/src/plle2_test.v @@ -87,7 +87,7 @@ wire rst = RST || !O_LOCKED; genvar i; generate for (i=0; i<6; i=i+1) begin - + reg [23:0] counter; always @(posedge clk[i] or posedge rst) diff --git a/minitests/timing/picosoc_noflash.v b/minitests/timing/picosoc_noflash.v index 0fab8e70..cd7442ac 100644 --- a/minitests/timing/picosoc_noflash.v +++ b/minitests/timing/picosoc_noflash.v @@ -94,11 +94,11 @@ module picosoc_noflash ( wire [31:0] simpleuart_reg_dat_do; wire simpleuart_reg_dat_wait; - assign mem_ready = + assign mem_ready = (iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel || simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait); - assign mem_rdata = + assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : progmem_ready ? progmem_rdata : ram_ready ? ram_rdata : @@ -106,7 +106,7 @@ module picosoc_noflash ( simpleuart_reg_div_sel ? simpleuart_reg_div_do : simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000; -`ifdef SIMULATION +`ifdef SIMULATION wire trace_valid; wire [35:0] trace_data; integer trace_file; @@ -121,7 +121,7 @@ module picosoc_noflash ( .ENABLE_MUL(1), .ENABLE_DIV(1), .ENABLE_IRQ(1), -`ifdef SIMULATION +`ifdef SIMULATION .ENABLE_IRQ_QREGS(0), .ENABLE_TRACE(1) `else diff --git a/prjxray/bitstream.py b/prjxray/bitstream.py index d4abf503..741d7909 100644 --- a/prjxray/bitstream.py +++ b/prjxray/bitstream.py @@ -17,7 +17,7 @@ bit_0002000f_079_06 Where: -0002000f: FDRI address -079: FDIR word number (0-100) --06: bit index (0-31) +-06: bit index (0-31) ''' diff --git a/prjxray/lms_solver.py b/prjxray/lms_solver.py index 3fe2f2a7..98dcef30 100755 --- a/prjxray/lms_solver.py +++ b/prjxray/lms_solver.py @@ -19,7 +19,7 @@ solved all at once (not recommended). For each tag a vector of weights is calculated. Each weight corresponds to one bit. Positive values indicate positive correlation and negative values negative -correlation. +correlation. Each weight vector is normalized so that maximum absolute weight is equal to one. @@ -557,7 +557,7 @@ def detect_candidates(X, th, norm=None): def compute_bit_correlations(tags_to_solve, bits_to_solve, segdata, W): """ - Basing on solution given in the matrix W returns a matrix C with + Basing on solution given in the matrix W returns a matrix C with correlation coefficients of each bit. Also returns a dict of dicts indexed by tag names and bit names with @@ -635,7 +635,7 @@ def compute_tag_stats(all_tags, segdata): Returns ------- - + A dict indexed by tag name with tuples containing 0 and 1 occurrence count. """ @@ -681,11 +681,11 @@ def build_address_map(tilegrid_file): ---------- tilegrid_file: - The tilegrid.json file/ + The tilegrid.json file/ Returns ------- - + A dict with lists of tile names. """ diff --git a/utils/blockwidth.py b/utils/blockwidth.py index 71573144..87d20bee 100755 --- a/utils/blockwidth.py +++ b/utils/blockwidth.py @@ -37,7 +37,7 @@ def gen_frame_writes(f): [Write Type=1 Address= 1 Length= 1 Reg="Frame Address"] Data in hex: - 1d + 1d ''' while True: diff --git a/utils/vtemplate b/utils/vtemplate index be8a1f6f..eccd0eaf 100755 --- a/utils/vtemplate +++ b/utils/vtemplate @@ -26,7 +26,7 @@ for l in txt.split('\n'): if m: names = m.group(5) aio = m.group(1) - + for name in names.split(','): name = name.strip() if not name: @@ -66,7 +66,7 @@ for l in txt.split('\n'): # input A0, A1, A2, A3, A4, A5, D, WCLK, WE; - + modinst = modname print '''\ diff --git a/vagrant/Vagrantfile b/vagrant/Vagrantfile index 7c71ae31..38480690 100644 --- a/vagrant/Vagrantfile +++ b/vagrant/Vagrantfile @@ -51,7 +51,7 @@ Vagrant.configure("2") do |config| s.inline = <<-SHELL export DISPLAY=:0 dconf write /org/gnome/desktop/screensaver/idle-activation-enabled false - dconf write /org/gnome/desktop/screensaver/lock-enabled false + dconf write /org/gnome/desktop/screensaver/lock-enabled false SHELL end