diff --git a/fuzzers/041-clk-hrow-pips/Makefile b/fuzzers/041-clk-hrow-pips/Makefile
index 1bb8bc01..4643f830 100644
--- a/fuzzers/041-clk-hrow-pips/Makefile
+++ b/fuzzers/041-clk-hrow-pips/Makefile
@@ -1,7 +1,15 @@
 export FUZDIR=$(shell pwd)
 PIP_TYPE?=clk_hrow
 PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
-MAKETODO_FLAGS=--no-l --pip-type clk_hrow_bot --seg-type clk_hrow_bot --re "[^\.]+\.CLK_HROW_CK_MUX_OUT_"
+ifeq (${XRAY_PART}, xc7z010clg400-1)
+# xc7z010clg400-1 is missing some side clock connections, so these bits cannot
+# be documented.
+TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_[LR][0-9]+\.CLK_HROW_.*[KR_][0-9]+"
+else
+TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_"
+endif
+
+MAKETODO_FLAGS=--no-l --pip-type clk_hrow_bot --seg-type clk_hrow_bot --re $(TODO_RE)
 N = 50
 
 # These PIPs all appear to be either a 0 or 2 bit solution.
diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py
index fe72f644..74c8d2de 100644
--- a/fuzzers/041-clk-hrow-pips/top.py
+++ b/fuzzers/041-clk-hrow-pips/top.py
@@ -255,9 +255,11 @@ module top();
                 c5=pll_clocks[5],
             ))
 
+    gclks = []
     for site in sorted(gen_sites("BUFGCTRL"),
                        key=util.create_xy_fun('BUFGCTRL_')):
         wire_name = 'clk_{}'.format(site)
+        gclks.append(wire_name)
 
         if not mmcm_pll_only:
             clock_sources.add_clock_source(wire_name, 'ANY')
@@ -274,12 +276,14 @@ module top();
                 wire_name=wire_name,
             ))
 
+    any_bufhce = False
     for tile_name, sites in gen_bufhce_sites():
         for site in sites:
             wire_name = clock_sources.get_random_source(site_to_cmt[site])
             if wire_name is None:
                 continue
 
+            any_bufhce = True
             print(
                 """
     (* KEEP, DONT_TOUCH, LOC = "{site}" *)
@@ -291,6 +295,22 @@ module top();
                     wire_name=wire_name,
                 ))
 
+    if not any_bufhce:
+        for tile_name, sites in gen_bufhce_sites():
+            for site in sites:
+                print(
+                    """
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    BUFHCE buf_{site} (
+        .I({wire_name})
+    );
+              """.format(
+                        site=site,
+                        wire_name=gclks[0],
+                    ))
+                break
+            break
+
     print("endmodule")