diff --git a/fuzzers/000-init-db/Makefile b/fuzzers/000-init-db/Makefile index e9294083..ebef99a1 100644 --- a/fuzzers/000-init-db/Makefile +++ b/fuzzers/000-init-db/Makefile @@ -36,7 +36,9 @@ DB_SIMPLE_L=$(addprefix segbits_,$(SEGBITS_L)) DB_SIMPLE_R=$(addprefix segbits_,$(SEGBITS_R)) DB_SIMPLE=\ $(addsuffix _l, $(DB_SIMPLE_LR) $(DB_SIMPLE_L)) \ - $(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) + $(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) \ + segbits_cmt_top_l_upper_t \ + segbits_cmt_top_r_upper_t \ BLOCK_RAM_EXTRA_FOR=\ mask_bram \ diff --git a/fuzzers/032-cmt-pll/generate.py b/fuzzers/032-cmt-pll/generate.py index 03deca99..8490180a 100644 --- a/fuzzers/032-cmt-pll/generate.py +++ b/fuzzers/032-cmt-pll/generate.py @@ -6,7 +6,20 @@ from prjxray.segmaker import Segmaker from prjxray import verilog +def bitfilter(frame, word): + if frame == 25 and word == 3121: + return False + + return True + + def bus_tags(segmk, ps, site): + for k in ps: + segmk.add_site_tag(site, 'param_' + k + '_' + str(ps[k]), 1) + + segmk.add_site_tag(site, 'DWE_CONNECTED', + ps['dwe_conn'].startswith('dwe_') or ps['dwe_conn'].startswith('den_')) + for reg, invert in [ ('RST', 1), ('PWRDWN', 1), @@ -19,10 +32,38 @@ def bus_tags(segmk, ps, site): else: segmk.add_site_tag(site, 'INV_' + reg, ps[opt]) + + for opt in ['OPTIMIZED', 'HIGH', 'LOW']: + if verilog.unquote(ps['BANDWIDTH']) == opt: + segmk.add_site_tag( + site, 'BANDWIDTH.' + opt, + 1) + elif verilog.unquote(ps['BANDWIDTH']) == 'LOW': + segmk.add_site_tag( + site, 'BANDWIDTH.' + opt, + 0) + for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL', 'INTERNAL']: + if site == "PLLE2_ADV_X0Y2" and opt == 'ZHOLD': + segmk.add_site_tag( + site, 'TOP.COMPENSATION.' + opt, + verilog.unquote(ps['COMPENSATION']) == opt) + else: + segmk.add_site_tag( + site, 'COMPENSATION.' + opt, + verilog.unquote(ps['COMPENSATION']) == opt) segmk.add_site_tag( - site, 'COMPENSATION.' + opt, - verilog.unquote(ps['COMPENSATION']) == opt) + site, 'COMPENSATION.Z_' + opt, + verilog.unquote(ps['COMPENSATION']) != opt) + + match = "TRUE" == verilog.unquote(ps['STARTUP_WAIT']) and \ + opt == verilog.unquote(ps['COMPENSATION']) + segmk.add_site_tag(site, "STARTUP_WAIT_AND_" + opt, + match) + + segmk.add_site_tag( + site, 'COMPENSATION.BUF_IN_OR_EXTERNAL', + verilog.unquote(ps['COMPENSATION']) in ['BUF_IN', 'EXTERNAL']) for param in ['CLKFBOUT_MULT']: paramadj = int(ps[param]) @@ -73,7 +114,7 @@ def run(): j = json.loads(l) bus_tags(segmk, j, j['site']) - segmk.compile() + segmk.compile(bitfilter=bitfilter) segmk.write() diff --git a/fuzzers/032-cmt-pll/top.py b/fuzzers/032-cmt-pll/top.py index 21d8b631..657e8fbb 100644 --- a/fuzzers/032-cmt-pll/top.py +++ b/fuzzers/032-cmt-pll/top.py @@ -29,6 +29,27 @@ def main(): params = { "site": site, + "dclk_conn": random.choice(( + "0", + "clk", + )), + "dwe_conn": random.choice(( + "", + "1", + "0", + "dwe_" + site, + "den_" + site, + )), + "den_conn": random.choice(( + "", + "1", + "0", + "den_" + site, + )), + "daddr4_conn": random.choice(( + "0", + "dwe_" + site, + )), "IS_RST_INVERTED": random.randint(0, 1), "IS_PWRDWN_INVERTED": @@ -63,12 +84,30 @@ def main(): 'EXTERNAL', 'INTERNAL', ))), + "BANDWIDTH": + verilog.quote( + random.choice(( + 'OPTIMIZED', + 'HIGH', + 'LOW', + ))), } f.write('%s\n' % (json.dumps(params))) print( """ + wire den_{site}; + wire dwe_{site}; + + LUT1 den_lut_{site} ( + .O(den_{site}) + ); + + LUT1 dwe_lut_{site} ( + .O(dwe_{site}) + ); + wire clkfbout_mult_{site}; wire clkout0_{site}; wire clkout1_{site}; @@ -91,7 +130,8 @@ def main(): .DIVCLK_DIVIDE({DIVCLK_DIVIDE}), .STARTUP_WAIT({STARTUP_WAIT}), .CLKOUT0_DUTY_CYCLE({CLKOUT0_DUTY_CYCLE}), - .COMPENSATION({COMPENSATION}) + .COMPENSATION({COMPENSATION}), + .BANDWIDTH({BANDWIDTH}) ) pll_{site} ( .CLKFBOUT(clkfbout_mult_{site}), .CLKOUT0(clkout0_{site}), @@ -107,13 +147,13 @@ def main(): .CLKIN1(clk), .CLKIN2(), .CLKINSEL(), - .DCLK(), - .DEN(), - .DWE(), + .DCLK({dclk_conn}), + .DEN({den_conn}), + .DWE({dwe_conn}), .PWRDWN(), .RST(), .DI(), - .DADDR()); + .DADDR({{7{{ {daddr4_conn} }} }})); (* KEEP, DONT_TOUCH *) FDRE reg_clkfbout_mult_{site} ( diff --git a/fuzzers/032-cmt-pll/write_pll_reg.py b/fuzzers/032-cmt-pll/write_pll_reg.py index 29cc71f5..49fdab5c 100644 --- a/fuzzers/032-cmt-pll/write_pll_reg.py +++ b/fuzzers/032-cmt-pll/write_pll_reg.py @@ -4,7 +4,9 @@ REGISTER_LAYOUT = { 'CLKOUT1': [ ('LOW_TIME', 6), ('HIGH_TIME', 6), - ('RESERVED', 1), + # This bit is the output enable bit, which is being detected as a pip + # bit, which is roughly correct. Leave this bit as a pip bit. + (None, 1), ('PHASE_MUX', 3), ], 'CLKOUT2': [ @@ -82,12 +84,12 @@ REGISTER_MAP.append(('LOCKREG1', 'LOCKREG1')) REGISTER_MAP.append(('LOCKREG2', 'LOCKREG2')) REGISTER_MAP.append(('LOCKREG3', 'LOCKREG3')) -for _ in range(0x28 - 0x1A + 1): +for _ in range(0x28 - 0x1A - 1): REGISTER_MAP.append(None) REGISTER_MAP.append(('POWER_REG', 'POWER_REG')) -for _ in range(0x4E - 0x28 + 1): +for _ in range(0x4E - 0x28 - 1): REGISTER_MAP.append(None) # 0x4E - 0x4F @@ -149,6 +151,9 @@ def passthrough_non_register_segbits(seg_in): print(l.strip()) continue + if feature_parts[2] == 'BANDWIDTH': + continue + if '[' not in feature_parts[2]: print(l.strip()) continue @@ -184,7 +189,7 @@ def output_registers(bit_offset): """ reg = RegisterAddress(frame_offsets=[28, 29], bit_offset=bit_offset) - for register in REGISTER_MAP: + for idx, register in enumerate(REGISTER_MAP): if register is None: for _ in range(16): reg.next_bit() @@ -196,35 +201,45 @@ def output_registers(bit_offset): simple_layout = len(layout_bits[0]) == 2 - for bit in range(16): - if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']: - print( - 'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format( - register_name, layout, bit, reg.next_bit())) - else: - print( - 'CMT_UPPER_T.PLLE2.{}[{}] {}'.format( - register_name, bit, reg.next_bit())) - - if False: + if True: bit_count = 0 if simple_layout: for field, width in layout_bits: for bit in range(width): + bit_count += 1 + + if field is None: + reg.next_bit() + continue + print( 'CMT_UPPER_T.PLLE2.{}_{}_{}[{}] {}'.format( register_name, layout, field, bit, reg.next_bit())) - bit_count += 1 else: for field, width, start_bit in layout_bits: for bit in range(width): + bit_count += 1 + + if field is None: + reg.next_bit() + continue + print( 'CMT_UPPER_T.PLLE2.{}[{}] {}'.format( field, start_bit + bit, reg.next_bit())) - bit_count += 1 assert bit_count == 16 + else: + for bit in range(16): + if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']: + print( + 'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format( + register_name, layout, bit, reg.next_bit())) + else: + print( + 'CMT_UPPER_T.PLLE2.{}[{}] {}'.format( + register_name, bit, reg.next_bit())) def main():