From b9031e0aeb62336958417843d0f94a9d0d382a5d Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Mon, 29 Oct 2018 21:05:14 -0700
Subject: [PATCH] Expand ROI to whole chip.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 database/artix7/settings.sh       |  2 +-
 fuzzers/005-tilegrid/generate.py  | 10 ++++++++--
 fuzzers/005-tilegrid/generate.tcl | 17 +++++++++++++----
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/database/artix7/settings.sh b/database/artix7/settings.sh
index aabe552c..06741abd 100644
--- a/database/artix7/settings.sh
+++ b/database/artix7/settings.sh
@@ -3,7 +3,7 @@ export XRAY_PART="xc7a50tfgg484-1"
 export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
 
 # All CLB's in X0Y2 CMT.
-export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
+export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
 export XRAY_ROI_GRID_X1="10"
 export XRAY_ROI_GRID_X2="58"
 # Y = 0 and Y  52 are VBRK rows, include them
diff --git a/fuzzers/005-tilegrid/generate.py b/fuzzers/005-tilegrid/generate.py
index bec31760..6454bd66 100644
--- a/fuzzers/005-tilegrid/generate.py
+++ b/fuzzers/005-tilegrid/generate.py
@@ -291,7 +291,10 @@ def create_segment_for_int_lr(
     else:
         assert False
 
-    if database[adjacent_tile]['type'].startswith('INT_INTERFACE_'):
+    if (
+       database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
+       database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_') or
+       database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
         # This INT_[LR] tile has no adjacent connectivity,
         # create a segment.
         add_segment(
@@ -303,7 +306,7 @@ def create_segment_for_int_lr(
             verbose=verbose,
         )
     else:
-        assert False
+        assert False, database[adjacent_tile]['type']
 
 
 def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
@@ -468,6 +471,9 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
                         grid_y -= 1
                         wordbase += 1
 
+                    if (grid_x, grid_y) not in tiles_by_grid:
+                        continue
+
                     dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
                     assert nolr(dst_tile['type']) == 'BRAM', dst_tile
 
diff --git a/fuzzers/005-tilegrid/generate.tcl b/fuzzers/005-tilegrid/generate.tcl
index 50410b84..d3a8c86f 100644
--- a/fuzzers/005-tilegrid/generate.tcl
+++ b/fuzzers/005-tilegrid/generate.tcl
@@ -11,7 +11,10 @@ proc make_project {} {
 
     create_pblock roi
     add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-    resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+    foreach roi "$::env(XRAY_ROI)" {
+        puts $roi
+        resize_pblock [get_pblocks roi] -add "$roi"
+    }
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
@@ -35,7 +38,8 @@ proc loc_luts {} {
         # 50 per column => 50, 100, 150, etc
         # ex: SLICE_X2Y50/A6LUT
         # Only take one of the CLBs within a slice
-        if [regexp "X.*[02468]Y.*[05]0/" $lut] {
+        if {[regexp "X.*[02468]Y(?:.*[05])?0/" $lut] || $lut == "SLICE_X44Y125/A6LUT" || $lut == "SLICE_X46Y125/A6LUT"} {
+            puts $lut
             set cell [get_cells roi/luts[$lut_index].lut]
             set_property LOC [get_sites -of_objects $lut] $cell
             set lut_index [expr $lut_index + 1]
@@ -60,7 +64,7 @@ proc loc_brams {} {
 
         # 10 per column => 10, 20, ,etc
         # ex: RAMB36_X0Y10/RAMBFIFO36E1
-        if [regexp "Y.*0/" $bram] {
+        if {[regexp "Y.*0/" $bram] || $bram == "RAMB36_X1Y25/RAMBFIFO36E1"} {
             set cell [get_cells roi/brams[$bram_index].bram]
             set_property LOC [get_sites -of_objects $bram] $cell
             set bram_index [expr $bram_index + 1]
@@ -130,9 +134,14 @@ proc write_brams { selected_brams } {
 proc run {} {
     make_project
     set selected_luts [loc_luts]
+    puts ""
+    puts ""
+    puts ""
+    puts ""
+    puts ""
     puts "Selected LUTs: [llength $selected_luts]"
     set selected_brams [loc_brams]
-    puts "Selected LUTs: [llength $selected_brams]"
+    puts "Selected BRAMs: [llength $selected_brams]"
 
     place_design
     route_design