diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index c614cb1d..2d897e5c 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -1,5 +1,3 @@ -# TODO: parallelize - FUZDIR=$(shell pwd) BUILD_DIR=$(FUZDIR)/build @@ -21,17 +19,18 @@ build/clb/deltas: build/bram/deltas: bash generate.sh build/bram bram -# FIXME: review IOB build/iob/deltas: bash generate.sh build/iob iob -build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb +build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json cd iob && $(MAKE) -# FIXME: review IOB +mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json + cd mmcm && $(MAKE) + build/tilegrid.json: generate_full.py build/tilegrid_tdb.json build/clb/deltas build/bram/deltas cd build && python3 ${FUZDIR}/generate_full.py \ --json-in tilegrid_tdb.json --json-out ${BUILD_DIR}/tilegrid.json \ @@ -46,6 +45,7 @@ run: clean: rm -rf build cd iob && $(MAKE) clean + cd mmcm && $(MAKE) clean .PHONY: database pushdb clean run diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py index 86fb595e..87e101e5 100644 --- a/fuzzers/005-tilegrid/add_tdb.py +++ b/fuzzers/005-tilegrid/add_tdb.py @@ -56,7 +56,9 @@ def load_db(fn): l = l.strip() # FIXME: add offset to name # IOB_X0Y101.DFRAME:27.DWORD:3.DBIT:3 00020027_003_03 - tagstr, addrstr = l.split(' ') + parts = l.split(' ') + assert len(parts) == 2, "Unresolved bit: %s" % l + tagstr, addrstr = parts frame, wordidx, bitidx = parse_addr(addrstr) bitidx_up = False @@ -79,8 +81,8 @@ def load_db(fn): # or detect the first delta auto and assert they are all the same if not bitidx_up: bitidx = 0 - assert bitidx == 0 - assert frame % 0x100 == 0, "Unaligned frame" + assert bitidx == 0, l + assert frame % 0x80 == 0, "Unaligned frame at 0x%08X" % frame yield (tile, frame, wordidx) @@ -92,7 +94,11 @@ def run(fn_in, fn_out, verbose=False): # FIXME: generate frames from part file (or equivilent) # See https://github.com/SymbiFlow/prjxray/issues/327 # FIXME: generate words from pitch - tdb_fns = [("iob/build/segbits_tilegrid.tdb", 42, 4)] + tdb_fns = [ + ("iob/build/segbits_tilegrid.tdb", 42, 4), + # FIXME: height + ("mmcm/build/segbits_tilegrid.tdb", 30, 4), + ] for (tdb_fn, frames, words) in tdb_fns: for (tile, frame, wordidx) in load_db(tdb_fn): tilej = database[tile] diff --git a/fuzzers/005-tilegrid/mmcm/Makefile b/fuzzers/005-tilegrid/mmcm/Makefile new file mode 100644 index 00000000..2e7ed7fd --- /dev/null +++ b/fuzzers/005-tilegrid/mmcm/Makefile @@ -0,0 +1,4 @@ +N ?= 2 +# Was expecting oneval 3, but bits might be inverted +GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 0 --dbit 15" +include ../fuzzaddr/common.mk diff --git a/fuzzers/005-tilegrid/mmcm/generate.tcl b/fuzzers/005-tilegrid/mmcm/generate.tcl new file mode 100644 index 00000000..cb0271e1 --- /dev/null +++ b/fuzzers/005-tilegrid/mmcm/generate.tcl @@ -0,0 +1,32 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + # Disable MMCM frequency etc sanity checks + set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}] + set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}] + set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}] + set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}] + set_property IS_ENABLED 0 [get_drc_checks {REQP-126}] + + place_design + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit +} + +run diff --git a/fuzzers/005-tilegrid/mmcm/top.py b/fuzzers/005-tilegrid/mmcm/top.py new file mode 100644 index 00000000..b63b441a --- /dev/null +++ b/fuzzers/005-tilegrid/mmcm/top.py @@ -0,0 +1,102 @@ +import os +import random +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray import verilog + + +def gen_sites(): + for tile_name, site_name, _site_type in util.get_roi().gen_sites( + ['MMCME2_ADV']): + yield tile_name, site_name + + +def write_params(params): + pinstr = 'tile,val,site\n' + for tile, (site, val) in sorted(params.items()): + pinstr += '%s,%s,%s\n' % (tile, val, site) + open('params.csv', 'w').write(pinstr) + + +def run(): + print( + ''' +module top(input clk, stb, di, output do); + localparam integer DIN_N = 8; + localparam integer DOUT_N = 8; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + ''') + + params = {} + # FIXME: can't LOC? + # only one for now, worry about later + sites = list(gen_sites()) + assert len(sites) == 1 + for (tile_name, site_name), isone in zip(sites, + util.gen_fuzz_states(len(sites))): + # 0 is invalid + # shift one bit, keeping LSB constant + CLKOUT1_DIVIDE = {0: 2, 1: 3}[isone] + params[tile_name] = (site_name, CLKOUT1_DIVIDE) + + print( + ''' + (* KEEP, DONT_TOUCH *) + MMCME2_ADV #(/*.LOC("%s"),*/ .CLKOUT1_DIVIDE(%u)) dut_%s( + .CLKFBOUT(), + .CLKFBOUTB(), + .CLKFBSTOPPED(), + .CLKINSTOPPED(), + .CLKOUT0(), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .DO(), + .DRDY(), + .LOCKED(), + .PSDONE(), + .CLKFBIN(clk), + .CLKIN1(clk), + .CLKIN2(clk), + .CLKINSEL(clk), + .DADDR(), + .DCLK(clk), + .DEN(), + .DI(), + .DWE(), + .PSCLK(clk), + .PSEN(), + .PSINCDEC(), + .PWRDWN(), + .RST()); +''' % (site_name, CLKOUT1_DIVIDE, site_name)) + + print("endmodule") + write_params(params) + + +if __name__ == '__main__': + run()