diff --git a/fuzzers/001-part-yaml/.gitignore b/fuzzers/001-part-yaml/.gitignore
new file mode 100644
index 00000000..9d456220
--- /dev/null
+++ b/fuzzers/001-part-yaml/.gitignore
@@ -0,0 +1,2 @@
+/specimen_*/
+*.yaml
diff --git a/fuzzers/001-part-yaml/Makefile b/fuzzers/001-part-yaml/Makefile
new file mode 100644
index 00000000..d66ec913
--- /dev/null
+++ b/fuzzers/001-part-yaml/Makefile
@@ -0,0 +1,17 @@
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+
+.PHONY: database pushdb clean $(SPECIMENS)
+
+$(SPECIMENS): Makefile.specimen
+	mkdir -p $@
+	$(MAKE) -C $@ -f ../Makefile.specimen
+
+database: $(SPECIMENS)
+	cp specimen_001/part.yaml ${XRAY_PART}.yaml
+
+pushdb:
+	cp ${XRAY_PART}.yaml ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ *.yaml
diff --git a/fuzzers/001-part-yaml/Makefile.specimen b/fuzzers/001-part-yaml/Makefile.specimen
new file mode 100644
index 00000000..e9a66664
--- /dev/null
+++ b/fuzzers/001-part-yaml/Makefile.specimen
@@ -0,0 +1,5 @@
+part.yaml: design.debug.bit
+	${XRAY_TOOLS_DIR}/gen_part_base_yaml $< > $@
+
+design.bit debug.perframecrc.bit design.debug.bit: ../generate.tcl
+	vivado -mode batch -source ../generate.tcl
diff --git a/fuzzers/001-part-yaml/generate.tcl b/fuzzers/001-part-yaml/generate.tcl
new file mode 100644
index 00000000..f95d3e2d
--- /dev/null
+++ b/fuzzers/001-part-yaml/generate.tcl
@@ -0,0 +1,33 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+
+# Write a normal bitstream that will do a singe FDRI write of all the frames.
+write_bitstream -force design.bit
+
+# Write a debug bitstream which writes each frame individually followed by
+# the frame address.  This shows where there are gaps in the frame address
+# space.
+set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
+write_bitstream -force design.debug.bit
+set_property BITSTREAM.GENERAL.DEBUGBITSTREAM NO [current_design]
+
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+write_bitstream -force design.perframecrc.bit
+set_property BITSTREAM.GENERAL.PERFRAMECRC NO [current_design]
diff --git a/fuzzers/001-part-yaml/top.v b/fuzzers/001-part-yaml/top.v
new file mode 100644
index 00000000..adbc3980
--- /dev/null
+++ b/fuzzers/001-part-yaml/top.v
@@ -0,0 +1,48 @@
+`define N 100
+
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 6;
+	localparam integer DOUT_N = `N;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+	roi roi (
+		.clk(clk),
+		.din(din),
+		.dout(dout)
+	);
+endmodule
+
+module roi(input clk, input [5:0] din, output [`N-1:0] dout);
+	genvar i;
+	generate
+		for (i = 0; i < `N; i = i+1) begin:is
+			LUT6 #(
+				.INIT(64'h8000_0000_0000_0001 + (i << 16))
+			) lut (
+				.I0(din[0]),
+				.I1(din[1]),
+				.I2(din[2]),
+				.I3(din[3]),
+				.I4(din[4]),
+				.I5(din[5]),
+				.O(dout[i])
+			);
+		end
+	endgenerate
+endmodule