diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 1de30d70..7a400432 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -2,5 +2,5 @@ 26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE -26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 28_126 29_123 29_125 -26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 28_2 28_4 29_1 +26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 +26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index d29f3064..c5751862 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -18,6 +18,7 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-105}] place_design route_design diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 691d3f0f..ffe962ef 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -226,10 +226,12 @@ IDELAYCTRL idelayctrl(); print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + clk1_conn = random.choice(["clk1", ""]) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) print( - 'ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' - % (param_str, i, i, i)) + 'ilogic_single #(%s) ilogic_%03d (.clk1(%s), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' + % (param_str, i, clk1_conn, i, i)) params["CHAINED"] = 0 params["TILE_NAME"] = tile_name