diff --git a/fuzzers/005-tilegrid/generate.py b/fuzzers/005-tilegrid/generate.py
index 4a70a2af..f7f9f6b6 100644
--- a/fuzzers/005-tilegrid/generate.py
+++ b/fuzzers/005-tilegrid/generate.py
@@ -460,13 +460,14 @@ def add_tile_bits(tile_db, baseaddr, offset, frames, words, height=None):
 
     # Index of first word used within each frame
     block["offset"] = offset
-    # Number of words consumed in each frame
-    block["words"] = words
 
     # related to words...
     # deprecated field? Don't worry about for now
-    if height is not None:
-        block["height"] = height
+    # DSP has some differences between height and words
+    block["words"] = words
+    if height is None:
+        height = words
+    block["height"] = height
 
 
 def db_add_bits(database, segments):
@@ -483,7 +484,7 @@ def db_add_bits(database, segments):
                     ("HCLK", "CLB_IO_CLK"): (26, 1, 1),
                     ("INT", "CLB_IO_CLK"): (28, 2, 2),
                     ("BRAM", "CLB_IO_CLK"): (28, 2, None),
-                    ("BRAM", "BLOCK_RAM"): (128, 5, None),
+                    ("BRAM", "BLOCK_RAM"): (128, 10, None),
                     ("DSP", "CLB_IO_CLK"): (28, 2, 10),
                     ("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
                     ("BRAM_INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
diff --git a/fuzzers/102-bram-data/.gitignore b/fuzzers/102-bram-data/.gitignore
new file mode 100644
index 00000000..932efba0
--- /dev/null
+++ b/fuzzers/102-bram-data/.gitignore
@@ -0,0 +1,2 @@
+/specimen_[0-9][0-9][0-9]/
+/seg_clbl[lm].segbits
diff --git a/fuzzers/102-bram-data/Makefile b/fuzzers/102-bram-data/Makefile
new file mode 100644
index 00000000..fd6c01c9
--- /dev/null
+++ b/fuzzers/102-bram-data/Makefile
@@ -0,0 +1,20 @@
+N := 8
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o seg_bramx.block_ram.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+
+pushdb:
+	${XRAY_MERGEDB} bram_l.block_ram seg_bramx.block_ram.segbits
+	${XRAY_MERGEDB} bram_r.block_ram seg_bramx.block_ram.segbits
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_*.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+
+.PHONY: database pushdb clean
+
diff --git a/fuzzers/102-bram-data/README.md b/fuzzers/102-bram-data/README.md
new file mode 100644
index 00000000..7350e13f
--- /dev/null
+++ b/fuzzers/102-bram-data/README.md
@@ -0,0 +1,4 @@
+Solves for BRAM data bits
+
+See workflow comments: https://github.com/SymbiFlow/prjxray/pull/180
+
diff --git a/fuzzers/102-bram-data/generate.py b/fuzzers/102-bram-data/generate.py
new file mode 100644
index 00000000..3fa86e8a
--- /dev/null
+++ b/fuzzers/102-bram-data/generate.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python3
+
+import sys, re, os
+
+sys.path.append("../../../utils/")
+from prjxray.segmaker import Segmaker
+
+c2i = {'0': 0, '1': 1}
+
+segmk = Segmaker("design.bits", verbose=True)
+segmk.set_def_bt('BLOCK_RAM')
+
+print("Loading tags")
+'''
+'''
+f = open('params.csv', 'r')
+f.readline()
+for l in f:
+    l = l.strip()
+    module, loc, pdata, data = l.split(',')
+
+    for i, d in enumerate(pdata):
+        # Keep dec convention used on LUT?
+        segmk.add_site_tag(loc, "INITP[%04d]" % i, c2i[d])
+    for i, d in enumerate(data):
+        # Keep dec convention used on LUT?
+        segmk.add_site_tag(loc, "INIT[%04d]" % i, c2i[d])
+
+segmk.compile()
+segmk.write()
diff --git a/fuzzers/102-bram-data/generate.sh b/fuzzers/102-bram-data/generate.sh
new file mode 100644
index 00000000..955c41b6
--- /dev/null
+++ b/fuzzers/102-bram-data/generate.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -ex
+
+source ${XRAY_GENHEADER}
+
+python3 ../top.py >top.v
+vivado -mode batch -source ../generate.tcl
+test -z "$(fgrep CRITICAL vivado.log)"
+
+for x in design*.bit; do
+	${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
+done
+
+python3 ../generate.py
+
diff --git a/fuzzers/102-bram-data/generate.tcl b/fuzzers/102-bram-data/generate.tcl
new file mode 100644
index 00000000..86162f92
--- /dev/null
+++ b/fuzzers/102-bram-data/generate.tcl
@@ -0,0 +1,26 @@
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
diff --git a/fuzzers/102-bram-data/top.py b/fuzzers/102-bram-data/top.py
new file mode 100644
index 00000000..b1c3d9f7
--- /dev/null
+++ b/fuzzers/102-bram-data/top.py
@@ -0,0 +1,229 @@
+'''
+Need coverage for the following:
+RAM32X1S_N
+RAM32X1D
+RAM32M
+RAM64X1S_N
+RAM64X1D_N
+RAM64M
+RAM128X1S_N
+RAM128X1D
+RAM256X1S
+SRL16E_N
+SRLC32E_N
+
+Note: LUT6 was added to try to simplify reduction, although it might not be needed
+'''
+
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+import sys
+
+
+def gen_bram18():
+    # yield "RAMB18_X%dY%d" % (x, y)
+    for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
+        ['RAMB18E1']):
+        yield site_name
+
+
+def gen_bram36():
+    #yield "RAMB36_X%dY%d" % (x, y)
+    for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
+        ['RAMBFIFO36E1']):
+        yield site_name
+
+
+DUTN = 10
+DIN_N = DUTN * 8
+DOUT_N = DUTN * 8
+
+verilog.top_harness(DIN_N, DOUT_N)
+
+f = open('params.csv', 'w')
+f.write('module,loc,pdata,data\n')
+print(
+    'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
+    (DIN_N - 1, DOUT_N - 1))
+
+
+def randbits(n):
+    return ''.join([random.choice(('0', '1')) for _x in range(n)])
+
+
+loci = 0
+
+
+def make(module, gen_locs, pdatan, datan):
+    global loci
+
+    for loci, loc in enumerate(gen_locs()):
+        if loci >= DUTN:
+            break
+
+        pdata = randbits(pdatan * 0x100)
+        data = randbits(datan * 0x100)
+
+        print('    %s #(' % module)
+        for i in range(pdatan):
+            print(
+                "        .INITP_%02X(256'b%s)," %
+                (i, pdata[i * 256:(i + 1) * 256]))
+        for i in range(datan):
+            print(
+                "        .INIT_%02X(256'b%s)," %
+                (i, data[i * 256:(i + 1) * 256]))
+        print('        .LOC("%s"))' % (loc, ))
+        print(
+            '            inst_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));'
+            % (loci, 8 * loci, 8 * loci))
+
+        f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
+        print('')
+        loci += 1
+    assert loci == DUTN
+
+
+#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
+make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
+
+f.close()
+print(
+    '''endmodule
+
+// ---------------------------------------------------------------------
+
+''')
+
+# RAMB18E1
+print(
+    '''
+module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "";
+    ''')
+for i in range(8):
+    print(
+        "    parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
+        % i)
+print('')
+for i in range(0x40):
+    print(
+        "    parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
+        % i)
+print('')
+print('''\
+    (* LOC=LOC *)
+    RAMB18E1 #(''')
+for i in range(8):
+    print('            .INITP_%02X(INITP_%02X),' % (i, i))
+print('')
+for i in range(0x40):
+    print('            .INIT_%02X(INIT_%02X),' % (i, i))
+print('')
+print(
+    '''
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST"),
+            .SIM_DEVICE("VIRTEX6")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+''')
+
+print(
+    '''
+
+module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "";
+    ''')
+for i in range(16):
+    print(
+        "    parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
+        % i)
+print('')
+for i in range(0x80):
+    print(
+        "    parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
+        % i)
+print('')
+print('''\
+    (* LOC=LOC *)
+    RAMB36E1 #(''')
+for i in range(16):
+    print('            .INITP_%02X(INITP_%02X),' % (i, i))
+print('')
+for i in range(0x80):
+    print('            .INIT_%02X(INIT_%02X),' % (i, i))
+print('')
+print(
+    '''
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST"),
+            .SIM_DEVICE("VIRTEX6")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+''')
diff --git a/minitests/bram/Makefile b/minitests/bram/Makefile
deleted file mode 100644
index 1d13e215..00000000
--- a/minitests/bram/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-include ../util/common.mk
diff --git a/minitests/bram/README.md b/minitests/bram/README.md
deleted file mode 100644
index 13bc497a..00000000
--- a/minitests/bram/README.md
+++ /dev/null
@@ -1,7 +0,0 @@
-# BRAM Minitest
-
-## Purpose
-Test to verify that all the ROM* primitives are just regular LUTs and not BRAMs with init values
-
-## Result
-Confirmed: floorplan shows as LUTs and no unknown bits observed
\ No newline at end of file
diff --git a/minitests/bram/.gitignore b/minitests/bram_basic/.gitignore
similarity index 100%
rename from minitests/bram/.gitignore
rename to minitests/bram_basic/.gitignore
diff --git a/minitests/bram_basic/Makefile b/minitests/bram_basic/Makefile
new file mode 100644
index 00000000..58acc9d6
--- /dev/null
+++ b/minitests/bram_basic/Makefile
@@ -0,0 +1,24 @@
+all:  build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff
+
+clean:
+	rm -rf build
+
+# Toggle one bit to locate where first BRAM data is
+build/roi_bramd_bit01.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bit01.diff PRJL=roi_bramd_bit0 PRJR=roi_bramd_bit1
+
+build/roi_bramd2_bit01.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd2_bit01.diff PRJL=roi_bramd_bit0 PRJR=roi_bramd2_bit1
+
+# Toggle all bits in a single BRAM data section
+build/roi_bramd_bits01.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bits01.diff PRJL=roi_bramd_bits0 PRJR=roi_bramd_bits1
+
+# Toggle one bit in each BRAM data section
+build/roi_bramds_bit01.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramds_bit01.diff PRJL=roi_bramds_bit0 PRJR=roi_bramds_bit1
+
+# Toggle one bit in each BRAM config section
+build/roi_bramis_bit01.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bramis_bit01.diff PRJL=roi_bramis_bit0 PRJR=roi_bramis_bit1
+
diff --git a/minitests/bram_basic/README.md b/minitests/bram_basic/README.md
new file mode 100644
index 00000000..2a99f236
--- /dev/null
+++ b/minitests/bram_basic/README.md
@@ -0,0 +1,8 @@
+# BRAM Minitest
+
+## Purpose
+Test basic BRAM instantiation and observe bitstream effects
+
+## Result
+BRAM configuration and data are in two very different areas of the bitstream
+
diff --git a/minitests/bram_basic/diff.mk b/minitests/bram_basic/diff.mk
new file mode 100644
index 00000000..b2c2ff60
--- /dev/null
+++ b/minitests/bram_basic/diff.mk
@@ -0,0 +1,11 @@
+all: $(OUT_DIFF)
+
+$(OUT_DIFF): build/$(PRJL)/design.bits build/$(PRJR)/design.bits
+	diff build/$(PRJL)/design.bits build/$(PRJR)/design.bits >$(OUT_DIFF) || true
+
+build/$(PRJL)/design.bits:
+	PROJECT=$(PRJL) bash runme.sh
+
+build/$(PRJR)/design.bits:
+	PROJECT=$(PRJR) bash runme.sh
+
diff --git a/minitests/bram/env.sh b/minitests/bram_basic/env.sh
similarity index 100%
rename from minitests/bram/env.sh
rename to minitests/bram_basic/env.sh
diff --git a/minitests/bram_basic/runme.sh b/minitests/bram_basic/runme.sh
new file mode 100644
index 00000000..9390d5ff
--- /dev/null
+++ b/minitests/bram_basic/runme.sh
@@ -0,0 +1,18 @@
+#!/bin/bash
+
+set -ex
+
+: "${PROJECT:?Need to set PROJECT non-empty}"
+
+# Create build dir
+export SRC_DIR=$PWD
+BUILD_DIR=build/$PROJECT
+mkdir -p $BUILD_DIR
+cd $BUILD_DIR
+
+export TOP_V=$SRC_DIR/top.v
+
+vivado -mode batch -source $SRC_DIR/runme.tcl
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
+test -z "$(fgrep CRITICAL vivado.log)"
+
diff --git a/minitests/bram_basic/runme.tcl b/minitests/bram_basic/runme.tcl
new file mode 100644
index 00000000..9674265d
--- /dev/null
+++ b/minitests/bram_basic/runme.tcl
@@ -0,0 +1,29 @@
+create_project -force -part $::env(XRAY_PART) design design
+#read_verilog $::env(SRC_DIR)/$::env(PROJECT).v
+read_verilog $::env(TOP_V)
+synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+
+# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
+write_bitstream -force design.bit
+
diff --git a/minitests/bram_basic/top.v b/minitests/bram_basic/top.v
new file mode 100644
index 00000000..2ae0328d
--- /dev/null
+++ b/minitests/bram_basic/top.v
@@ -0,0 +1,567 @@
+/*
+ROM128X1: 128-Deep by 1-Wide ROM
+ROM256X1: 256-Deep by 1-Wide ROM
+ROM32X1: 32-Deep by 1-Wide ROM
+ROM64X1: 64-Deep by 1-Wide ROM
+*/
+
+`ifndef ROI
+ERROR: must set ROI
+`endif
+
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 256;
+	localparam integer DOUT_N = 256;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+    `ROI
+	    roi (
+		.clk(clk),
+		.din(din),
+		.dout(dout)
+	);
+endmodule
+
+/******************************************************************************
+DATA ROI
+******************************************************************************/
+
+/******************************************************************************
+Toggle a single data bit to locate a single instance
+******************************************************************************/
+module roi_bramd_bit0(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bramd_bit1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bramd2_bit1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(256'b10), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bram18d_bit0(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bram18d_bit1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+/******************************************************************************
+Toggle all bits to show the size of the data section
+******************************************************************************/
+
+module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+/******************************************************************************
+Toggle all the data bits in the ROI to show pitch between entries
+******************************************************************************/
+
+module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r3(.clk(clk), .din(din[  24 +: 8]), .dout(dout[  24 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r4(.clk(clk), .din(din[  32 +: 8]), .dout(dout[  32 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r5(.clk(clk), .din(din[  40 +: 8]), .dout(dout[  40 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r6(.clk(clk), .din(din[  48 +: 8]), .dout(dout[  48 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r7(.clk(clk), .din(din[  56 +: 8]), .dout(dout[  56 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r8(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}))
+            r9(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
+endmodule
+
+module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r3(.clk(clk), .din(din[  24 +: 8]), .dout(dout[  24 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r4(.clk(clk), .din(din[  32 +: 8]), .dout(dout[  32 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r5(.clk(clk), .din(din[  40 +: 8]), .dout(dout[  40 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r6(.clk(clk), .din(din[  48 +: 8]), .dout(dout[  48 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r7(.clk(clk), .din(din[  56 +: 8]), .dout(dout[  56 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r8(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b1), .INIT({256{1'b0}}))
+            r9(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
+endmodule
+
+/******************************************************************************
+CONFIG ROI
+******************************************************************************/
+
+module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r3(.clk(clk), .din(din[  24 +: 8]), .dout(dout[  24 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r4(.clk(clk), .din(din[  32 +: 8]), .dout(dout[  32 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r5(.clk(clk), .din(din[  40 +: 8]), .dout(dout[  40 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r6(.clk(clk), .din(din[  48 +: 8]), .dout(dout[  48 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r7(.clk(clk), .din(din[  56 +: 8]), .dout(dout[  56 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r8(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
+            r9(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
+endmodule
+
+module roi_bramis_bit1(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r3(.clk(clk), .din(din[  24 +: 8]), .dout(dout[  24 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r4(.clk(clk), .din(din[  32 +: 8]), .dout(dout[  32 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r5(.clk(clk), .din(din[  40 +: 8]), .dout(dout[  40 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r6(.clk(clk), .din(din[  48 +: 8]), .dout(dout[  48 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r7(.clk(clk), .din(din[  56 +: 8]), .dout(dout[  56 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r8(.clk(clk), .din(din[  64 +: 8]), .dout(dout[  64 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r9(.clk(clk), .din(din[  72 +: 8]), .dout(dout[  72 +: 8]));
+endmodule
+
+/******************************************************************************
+Misc ROI
+******************************************************************************/
+
+//ram_RAMB36E1 too much churn to be useful to compare vs above
+//instead lets change something more subtle
+// ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND: roi/r0/ram programming
+// per UG473 requires that for SDP mode the WEA bus must be unconnected or tied to GND.
+module roi_bramd_sdp(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .RAM_MODE("SDP"))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bramd_inv(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bram36_0s(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+module roi_bram36_1s(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+/*
+Place everything into first tile
+This is invalid since 18/36 share resources
+*/
+module roi_invalid(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT({256{1'b1}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT({256{1'b1}}))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT({256{1'b1}}))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+endmodule
+
+//HCK test
+//XXX: what specifically was this testing?
+module roi_hck(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT({256{1'b1}}))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT({256{1'b1}}))
+            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+    //HCK
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT({256{1'b1}}))
+            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
+    ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT({256{1'b1}}))
+            r3(.clk(clk), .din(din[  24 +: 8]), .dout(dout[  24 +: 8]));
+
+endmodule
+
+/******************************************************************************
+Library
+******************************************************************************/
+
+
+/*
+Site RAMB18_X0Y42
+Pushed it outside the pblock
+lets extend pblock
+
+for i in xrange(0x08): print '.INITP_%02X(INIT),' % i
+for i in xrange(0x40): print '.INIT_%02X(INIT),' % i
+*/
+module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "";
+    parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter RAM_MODE = "TDP";
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+
+    (* LOC=LOC *)
+    RAMB18E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+
+            .INIT_00(INIT0),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE(RAM_MODE),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST"),
+            .SIM_DEVICE("VIRTEX6")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+
+endmodule
+
+module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "";
+    parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT0),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST"),
+            .SIM_DEVICE("VIRTEX6")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/.gitignore b/minitests/bram_diff/.gitignore
new file mode 100644
index 00000000..4e8ac423
--- /dev/null
+++ b/minitests/bram_diff/.gitignore
@@ -0,0 +1,10 @@
+/.Xil/
+/design_*/
+/design_*.dcp
+/design_*.bit
+/design_*.bits
+/design_*.segd
+/fixed.xdc
+/usage_statistics_webtalk.*
+/vivado*
+/*.seg
diff --git a/minitests/bram_diff/Makefile b/minitests/bram_diff/Makefile
new file mode 100644
index 00000000..774832ac
--- /dev/null
+++ b/minitests/bram_diff/Makefile
@@ -0,0 +1,8 @@
+all:
+	bash runme.sh
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil design_* *.xdc
+
+.PHONY: all clean
+
diff --git a/minitests/bram_diff/README.md b/minitests/bram_diff/README.md
new file mode 100644
index 00000000..0c58a42d
--- /dev/null
+++ b/minitests/bram_diff/README.md
@@ -0,0 +1,72 @@
+Some quick tests to understand BRAM configuration
+Written before segments were fully developed, so this preliminary writeup is a bit coarse
+
+Basically all the RAMB36 configuration tests show two bit flips
+This indicates that RAMB18 and RAMB36 are fully indepdnently configurable
+SDP vs TDP was a lot more complicated, needs more investigation
+
+Note: tested on a7 after sourcing env.sh. k7 would likely also work
+
+
+Raw data
+
+set_property LOC RAMB36_X0Y21 [get_cells ram]
+
+design_CLKARDCLK_INV.bits
+  < bit_0002031b_013_11
+  < bit_0002031b_016_21
+
+design_CLKBWRCLK_INV.bits
+  < bit_0002031b_013_13
+  < bit_0002031b_016_19
+
+design_CLKARDCLK_INV.bits
+  < bit_0002031b_013_11
+  < bit_0002031b_016_21
+
+design_CLKBWRCLK_INV.bits
+  < bit_0002031b_013_13
+  < bit_0002031b_016_19
+
+design_ENARDEN_INV.bits
+  < bit_0002031b_013_16
+  < bit_0002031b_016_16
+
+design_ENBWREN_INV.bits
+  < bit_0002031b_013_19
+  < bit_0002031b_016_13
+
+design_RSTRAMARSTRAM_INV.bits
+  < bit_0002031b_013_20
+  < bit_0002031b_016_12
+
+design_RSTRAMB_INV.bits
+  < bit_0002031b_013_21
+  < bit_0002031b_016_11
+
+design_RSTREGARSTREG_INV.bits
+  < bit_0002031b_013_24
+  < bit_0002031b_016_08
+
+design_RSTREGB_INV.bits
+  < bit_0002031b_013_27
+  < bit_0002031b_016_05
+
+design_WRITE_MODE_A_NC.bits
+  > bit_0002031b_012_00
+  > bit_0002031b_018_00
+
+design_WRITE_MODE_A_RF.bits
+  > bit_0002031b_011_24
+  > bit_0002031b_018_08
+
+TDP vs SDP probably does routing changes, leading to a lot of bit flips
+design_RAM_MODE_SDP.bits
+  > bit_00020282_010_05
+  > bit_00020284_010_06
+  < bit_00020289_010_04
+  < bit_0002028f_010_04
+  > bit_00020300_014_11
+  < bit_00020300_016_27
+  > bit_00020300_016_25
+...etc
diff --git a/minitests/bram_diff/env.sh b/minitests/bram_diff/env.sh
new file mode 100644
index 00000000..9d56a031
--- /dev/null
+++ b/minitests/bram_diff/env.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+export XRAY_ROI=SLICE_X6Y100:SLICE_X27Y149
+export XRAY_ROI_FRAMES=0x00000000:0xFFFFFFFF
+
diff --git a/minitests/bram_diff/runme.sh b/minitests/bram_diff/runme.sh
new file mode 100755
index 00000000..bc3ed9a4
--- /dev/null
+++ b/minitests/bram_diff/runme.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -ex
+vivado -mode batch -source runme.tcl
+for bit in $(ls *.bit); do
+    ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${bit}s -z -y $bit
+done
+
+for b in $(ls *.bits); do
+    echo
+    echo $b
+    diff design_ref.bits $b |grep '[<>]' |sed 's/^/  /'
+done
diff --git a/minitests/bram_diff/runme.tcl b/minitests/bram_diff/runme.tcl
new file mode 100644
index 00000000..a7d1b27b
--- /dev/null
+++ b/minitests/bram_diff/runme.tcl
@@ -0,0 +1,61 @@
+
+create_project -force -part $::env(XRAY_PART) design_fdre design_fdre
+read_verilog top_ref.v
+
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+
+set_property LOC RAMB36_X0Y21 [get_cells ram]
+
+route_design
+
+#set_property IS_ROUTE_FIXED 1 [get_nets -hierarchical]
+set_property IS_LOC_FIXED 1 [get_cells -hierarchical]
+set_property IS_BEL_FIXED 1 [get_cells -hierarchical]
+
+write_xdc -force fixed.xdc
+
+write_checkpoint -force design_ref.dcp
+write_bitstream -force design_ref.bit
+
+close_project
+
+foreach variant {CLKARDCLK_INV CLKBWRCLK_INV ENARDEN_INV ENBWREN_INV RSTRAMARSTRAM_INV RSTRAMB_INV RSTREGARSTREG_INV RSTREGB_INV RAM_MODE_SDP WRITE_MODE_A_NC WRITE_MODE_A_RF} {
+    create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
+    read_verilog top_${variant}.v
+    read_xdc fixed.xdc
+
+    synth_design -top top
+
+    if {0} {
+        set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+        set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+        set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+        set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+        set_property CFGBVS VCCO [current_design]
+        set_property CONFIG_VOLTAGE 3.3 [current_design]
+        set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+        set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+    }
+
+    place_design
+    route_design
+
+    write_checkpoint -force design_${variant}.dcp
+    write_bitstream -force design_${variant}.bit
+
+    close_project
+}
+
diff --git a/minitests/bram_diff/top_CLKARDCLK_INV.v b/minitests/bram_diff/top_CLKARDCLK_INV.v
new file mode 100644
index 00000000..cfb6e5d0
--- /dev/null
+++ b/minitests/bram_diff/top_CLKARDCLK_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b1),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_CLKBWRCLK_INV.v b/minitests/bram_diff/top_CLKBWRCLK_INV.v
new file mode 100644
index 00000000..c12c7892
--- /dev/null
+++ b/minitests/bram_diff/top_CLKBWRCLK_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b1),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_ENARDEN_INV.v b/minitests/bram_diff/top_ENARDEN_INV.v
new file mode 100644
index 00000000..8c19c062
--- /dev/null
+++ b/minitests/bram_diff/top_ENARDEN_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b1),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_ENBWREN_INV.v b/minitests/bram_diff/top_ENBWREN_INV.v
new file mode 100644
index 00000000..7d2f9d3a
--- /dev/null
+++ b/minitests/bram_diff/top_ENBWREN_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b1),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_RAM_MODE_SDP.v b/minitests/bram_diff/top_RAM_MODE_SDP.v
new file mode 100644
index 00000000..1ae5b4ac
--- /dev/null
+++ b/minitests/bram_diff/top_RAM_MODE_SDP.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("SDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_RSTRAMARSTRAM_INV.v b/minitests/bram_diff/top_RSTRAMARSTRAM_INV.v
new file mode 100644
index 00000000..048a0d71
--- /dev/null
+++ b/minitests/bram_diff/top_RSTRAMARSTRAM_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b1),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_RSTRAMB_INV.v b/minitests/bram_diff/top_RSTRAMB_INV.v
new file mode 100644
index 00000000..bba5e9e0
--- /dev/null
+++ b/minitests/bram_diff/top_RSTRAMB_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b1),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_RSTREGARSTREG_INV.v b/minitests/bram_diff/top_RSTREGARSTREG_INV.v
new file mode 100644
index 00000000..0df37542
--- /dev/null
+++ b/minitests/bram_diff/top_RSTREGARSTREG_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b1),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_RSTREGB_INV.v b/minitests/bram_diff/top_RSTREGB_INV.v
new file mode 100644
index 00000000..067d1561
--- /dev/null
+++ b/minitests/bram_diff/top_RSTREGB_INV.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b1),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("WRITE_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_WRITE_MODE_A_NC.v b/minitests/bram_diff/top_WRITE_MODE_A_NC.v
new file mode 100644
index 00000000..5f768984
--- /dev/null
+++ b/minitests/bram_diff/top_WRITE_MODE_A_NC.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("TDP"),
+            .WRITE_MODE_A("NO_CHANGE"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram_diff/top_WRITE_MODE_A_RF.v b/minitests/bram_diff/top_WRITE_MODE_A_RF.v
new file mode 100644
index 00000000..efb8d2d8
--- /dev/null
+++ b/minitests/bram_diff/top_WRITE_MODE_A_RF.v
@@ -0,0 +1,213 @@
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+
+
+
+
+    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
+    RAMB36E1 #(
+            .INITP_00(INIT),
+            .INITP_01(INIT),
+            .INITP_02(INIT),
+            .INITP_03(INIT),
+            .INITP_04(INIT),
+            .INITP_05(INIT),
+            .INITP_06(INIT),
+            .INITP_07(INIT),
+            .INITP_08(INIT),
+            .INITP_09(INIT),
+            .INITP_0A(INIT),
+            .INITP_0B(INIT),
+            .INITP_0C(INIT),
+            .INITP_0D(INIT),
+            .INITP_0E(INIT),
+            .INITP_0F(INIT),
+
+            .INIT_00(INIT),
+            .INIT_01(INIT),
+            .INIT_02(INIT),
+            .INIT_03(INIT),
+            .INIT_04(INIT),
+            .INIT_05(INIT),
+            .INIT_06(INIT),
+            .INIT_07(INIT),
+            .INIT_08(INIT),
+            .INIT_09(INIT),
+            .INIT_0A(INIT),
+            .INIT_0B(INIT),
+            .INIT_0C(INIT),
+            .INIT_0D(INIT),
+            .INIT_0E(INIT),
+            .INIT_0F(INIT),
+            .INIT_10(INIT),
+            .INIT_11(INIT),
+            .INIT_12(INIT),
+            .INIT_13(INIT),
+            .INIT_14(INIT),
+            .INIT_15(INIT),
+            .INIT_16(INIT),
+            .INIT_17(INIT),
+            .INIT_18(INIT),
+            .INIT_19(INIT),
+            .INIT_1A(INIT),
+            .INIT_1B(INIT),
+            .INIT_1C(INIT),
+            .INIT_1D(INIT),
+            .INIT_1E(INIT),
+            .INIT_1F(INIT),
+            .INIT_20(INIT),
+            .INIT_21(INIT),
+            .INIT_22(INIT),
+            .INIT_23(INIT),
+            .INIT_24(INIT),
+            .INIT_25(INIT),
+            .INIT_26(INIT),
+            .INIT_27(INIT),
+            .INIT_28(INIT),
+            .INIT_29(INIT),
+            .INIT_2A(INIT),
+            .INIT_2B(INIT),
+            .INIT_2C(INIT),
+            .INIT_2D(INIT),
+            .INIT_2E(INIT),
+            .INIT_2F(INIT),
+            .INIT_30(INIT),
+            .INIT_31(INIT),
+            .INIT_32(INIT),
+            .INIT_33(INIT),
+            .INIT_34(INIT),
+            .INIT_35(INIT),
+            .INIT_36(INIT),
+            .INIT_37(INIT),
+            .INIT_38(INIT),
+            .INIT_39(INIT),
+            .INIT_3A(INIT),
+            .INIT_3B(INIT),
+            .INIT_3C(INIT),
+            .INIT_3D(INIT),
+            .INIT_3E(INIT),
+            .INIT_3F(INIT),
+
+            .INIT_40(INIT),
+            .INIT_41(INIT),
+            .INIT_42(INIT),
+            .INIT_43(INIT),
+            .INIT_44(INIT),
+            .INIT_45(INIT),
+            .INIT_46(INIT),
+            .INIT_47(INIT),
+            .INIT_48(INIT),
+            .INIT_49(INIT),
+            .INIT_4A(INIT),
+            .INIT_4B(INIT),
+            .INIT_4C(INIT),
+            .INIT_4D(INIT),
+            .INIT_4E(INIT),
+            .INIT_4F(INIT),
+            .INIT_50(INIT),
+            .INIT_51(INIT),
+            .INIT_52(INIT),
+            .INIT_53(INIT),
+            .INIT_54(INIT),
+            .INIT_55(INIT),
+            .INIT_56(INIT),
+            .INIT_57(INIT),
+            .INIT_58(INIT),
+            .INIT_59(INIT),
+            .INIT_5A(INIT),
+            .INIT_5B(INIT),
+            .INIT_5C(INIT),
+            .INIT_5D(INIT),
+            .INIT_5E(INIT),
+            .INIT_5F(INIT),
+            .INIT_60(INIT),
+            .INIT_61(INIT),
+            .INIT_62(INIT),
+            .INIT_63(INIT),
+            .INIT_64(INIT),
+            .INIT_65(INIT),
+            .INIT_66(INIT),
+            .INIT_67(INIT),
+            .INIT_68(INIT),
+            .INIT_69(INIT),
+            .INIT_6A(INIT),
+            .INIT_6B(INIT),
+            .INIT_6C(INIT),
+            .INIT_6D(INIT),
+            .INIT_6E(INIT),
+            .INIT_6F(INIT),
+            .INIT_70(INIT),
+            .INIT_71(INIT),
+            .INIT_72(INIT),
+            .INIT_73(INIT),
+            .INIT_74(INIT),
+            .INIT_75(INIT),
+            .INIT_76(INIT),
+            .INIT_77(INIT),
+            .INIT_78(INIT),
+            .INIT_79(INIT),
+            .INIT_7A(INIT),
+            .INIT_7B(INIT),
+            .INIT_7C(INIT),
+            .INIT_7D(INIT),
+            .INIT_7E(INIT),
+            .INIT_7F(INIT),
+
+            .IS_CLKARDCLK_INVERTED(1'b0),
+            .IS_CLKBWRCLK_INVERTED(1'b0),
+            .IS_ENARDEN_INVERTED(1'b0),
+            .IS_ENBWREN_INVERTED(1'b0),
+            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+            .IS_RSTRAMB_INVERTED(1'b0),
+            .IS_RSTREGARSTREG_INVERTED(1'b0),
+            .IS_RSTREGB_INVERTED(1'b0),
+            .RAM_MODE("READ_FIRST"),
+            .WRITE_MODE_A("READ_FIRST"),
+            .WRITE_MODE_B("WRITE_FIRST")
+        ) ram (
+            .CLKARDCLK(din[0]),
+            .CLKBWRCLK(din[1]),
+            .ENARDEN(din[2]),
+            .ENBWREN(din[3]),
+            .REGCEAREGCE(din[4]),
+            .REGCEB(din[5]),
+            .RSTRAMARSTRAM(din[6]),
+            .RSTRAMB(din[7]),
+            .RSTREGARSTREG(din[0]),
+            .RSTREGB(din[1]),
+            .ADDRARDADDR(din[2]),
+            .ADDRBWRADDR(din[3]),
+            .DIADI(din[4]),
+            .DIBDI(din[5]),
+            .DIPADIP(din[6]),
+            .DIPBDIP(din[7]),
+            .WEA(din[0]),
+            .WEBWE(din[1]),
+            .DOADO(dout[0]),
+            .DOBDO(dout[1]),
+            .DOPADOP(dout[2]),
+            .DOPBDOP(dout[3]));
+endmodule
+
diff --git a/minitests/bram/top.v b/minitests/bram_diff/top_ref.v
similarity index 51%
rename from minitests/bram/top.v
rename to minitests/bram_diff/top_ref.v
index 08915395..f0660857 100644
--- a/minitests/bram/top.v
+++ b/minitests/bram_diff/top_ref.v
@@ -1,13 +1,6 @@
-/*
-ROM128X1: 128-Deep by 1-Wide ROM
-ROM256X1: 256-Deep by 1-Wide ROM
-ROM32X1: 32-Deep by 1-Wide ROM
-ROM64X1: 64-Deep by 1-Wide ROM
-*/
-
 module top(input clk, stb, di, output do);
-	localparam integer DIN_N = 256;
-	localparam integer DOUT_N = 256;
+	localparam integer DIN_N = 8;
+	localparam integer DOUT_N = 8;
 
 	reg [DIN_N-1:0] din;
 	wire [DOUT_N-1:0] dout;
@@ -26,169 +19,14 @@ module top(input clk, stb, di, output do);
 
 	assign do = dout_shr[DOUT_N-1];
 
-	roi roi (
-		.clk(clk),
-		.din(din),
-		.dout(dout)
-	);
-endmodule
 
-/*
-One BRAM per tile
-*/
-module roi(input clk, input [255:0] din, output [255:0] dout);
-    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}}))
-            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
-    ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b1), .INIT({256{1'b0}}))
-            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
-    ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b1), .INIT({256{1'b0}}))
-            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));    
-endmodule
 
-/*
-Place everything into first tile
-This is invalid since 18/36 share resources
-*/
-module roi_invalid(input clk, input [255:0] din, output [255:0] dout);
-    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT({256{1'b1}}))
-            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
-    ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT({256{1'b1}}))
-            r1(.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
-    ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT({256{1'b1}}))
-            r2(.clk(clk), .din(din[  16 +: 8]), .dout(dout[  16 +: 8]));
-endmodule
 
-/*
-Site RAMB18_X0Y42
-Pushed it outside the pblock
-lets extend pblock
 
-for i in xrange(0x08): print '.INITP_%02X(INIT),' % i
-for i in xrange(0x40): print '.INIT_%02X(INIT),' % i
-*/
-module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
-    parameter LOC = "";
-    parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
-    (* LOC=LOC *)
-    RAMB18E1 #(
-            .INITP_00(INIT),
-            .INITP_01(INIT),
-            .INITP_02(INIT),
-            .INITP_03(INIT),
-            .INITP_04(INIT),
-            .INITP_05(INIT),
-            .INITP_06(INIT),
-            .INITP_07(INIT),
-
-            .INIT_00(INIT0),
-            .INIT_01(INIT),
-            .INIT_02(INIT),
-            .INIT_03(INIT),
-            .INIT_04(INIT),
-            .INIT_05(INIT),
-            .INIT_06(INIT),
-            .INIT_07(INIT),
-            .INIT_08(INIT),
-            .INIT_09(INIT),
-            .INIT_0A(INIT),
-            .INIT_0B(INIT),
-            .INIT_0C(INIT),
-            .INIT_0D(INIT),
-            .INIT_0E(INIT),
-            .INIT_0F(INIT),
-            .INIT_10(INIT),
-            .INIT_11(INIT),
-            .INIT_12(INIT),
-            .INIT_13(INIT),
-            .INIT_14(INIT),
-            .INIT_15(INIT),
-            .INIT_16(INIT),
-            .INIT_17(INIT),
-            .INIT_18(INIT),
-            .INIT_19(INIT),
-            .INIT_1A(INIT),
-            .INIT_1B(INIT),
-            .INIT_1C(INIT),
-            .INIT_1D(INIT),
-            .INIT_1E(INIT),
-            .INIT_1F(INIT),
-            .INIT_20(INIT),
-            .INIT_21(INIT),
-            .INIT_22(INIT),
-            .INIT_23(INIT),
-            .INIT_24(INIT),
-            .INIT_25(INIT),
-            .INIT_26(INIT),
-            .INIT_27(INIT),
-            .INIT_28(INIT),
-            .INIT_29(INIT),
-            .INIT_2A(INIT),
-            .INIT_2B(INIT),
-            .INIT_2C(INIT),
-            .INIT_2D(INIT),
-            .INIT_2E(INIT),
-            .INIT_2F(INIT),
-            .INIT_30(INIT),
-            .INIT_31(INIT),
-            .INIT_32(INIT),
-            .INIT_33(INIT),
-            .INIT_34(INIT),
-            .INIT_35(INIT),
-            .INIT_36(INIT),
-            .INIT_37(INIT),
-            .INIT_38(INIT),
-            .INIT_39(INIT),
-            .INIT_3A(INIT),
-            .INIT_3B(INIT),
-            .INIT_3C(INIT),
-            .INIT_3D(INIT),
-            .INIT_3E(INIT),
-            .INIT_3F(INIT),
-
-            .IS_CLKARDCLK_INVERTED(1'b0),
-            .IS_CLKBWRCLK_INVERTED(1'b0),
-            .IS_ENARDEN_INVERTED(1'b0),
-            .IS_ENBWREN_INVERTED(1'b0),
-            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
-            .IS_RSTRAMB_INVERTED(1'b0),
-            .IS_RSTREGARSTREG_INVERTED(1'b0),
-            .IS_RSTREGB_INVERTED(1'b0),
-            .RAM_MODE("TDP"),
-            .WRITE_MODE_A("WRITE_FIRST"),
-            .WRITE_MODE_B("WRITE_FIRST"),
-            .SIM_DEVICE("VIRTEX6")
-        ) ram (
-            .CLKARDCLK(din[0]),
-            .CLKBWRCLK(din[1]),
-            .ENARDEN(din[2]),
-            .ENBWREN(din[3]),
-            .REGCEAREGCE(din[4]),
-            .REGCEB(din[5]),
-            .RSTRAMARSTRAM(din[6]),
-            .RSTRAMB(din[7]),
-            .RSTREGARSTREG(din[0]),
-            .RSTREGB(din[1]),
-            .ADDRARDADDR(din[2]),
-            .ADDRBWRADDR(din[3]),
-            .DIADI(din[4]),
-            .DIBDI(din[5]),
-            .DIPADIP(din[6]),
-            .DIPBDIP(din[7]),
-            .WEA(din[0]),
-            .WEBWE(din[1]),
-            .DOADO(dout[0]),
-            .DOBDO(dout[1]),
-            .DOPADOP(dout[2]),
-            .DOPBDOP(dout[3]));
-
-endmodule
-
-module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
-    parameter LOC = "";
     parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	//(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	(* KEEP, DONT_TOUCH *)
     RAMB36E1 #(
             .INITP_00(INIT),
             .INITP_01(INIT),
@@ -347,8 +185,7 @@ module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
             .IS_RSTREGB_INVERTED(1'b0),
             .RAM_MODE("TDP"),
             .WRITE_MODE_A("WRITE_FIRST"),
-            .WRITE_MODE_B("WRITE_FIRST"),
-            .SIM_DEVICE("VIRTEX6")
+            .WRITE_MODE_B("WRITE_FIRST")
         ) ram (
             .CLKARDCLK(din[0]),
             .CLKBWRCLK(din[1]),
diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py
index 33fe1354..04106bd0 100644
--- a/prjxray/segmaker.py
+++ b/prjxray/segmaker.py
@@ -60,6 +60,14 @@ class Segmaker:
         # output after compiling
         self.segments_by_type = None
 
+        # hacky...improve if we encounter this more
+        self.def_bt = 'CLB_IO_CLK'
+
+    def set_def_bt(self, block_type):
+        '''Set default block type when more than one block present'''
+        assert block_type in BLOCK_TYPES
+        self.def_bt = block_type
+
     def load_grid(self):
         '''Load self.grid holding tile addresses'''
         with open(os.path.join(self.db_root, "tilegrid.json"), "r") as f:
@@ -148,6 +156,7 @@ class Segmaker:
                     "tags": dict(),
                     # verify new entries match this
                     "offset": bitj["offset"],
+                    "height": bitj["height"],
                     "words": bitj["words"],
                     "frames": bitj["frames"],
                 })
@@ -185,6 +194,7 @@ class Segmaker:
                 else:
                     segment = segments[segname]
                     assert segment["offset"] == bitj["offset"]
+                    assert segment["height"] == bitj["height"]
                     assert segment["words"] == bitj["words"]
                     assert segment["frames"] == bitj["frames"]
                     return segment
@@ -200,20 +210,29 @@ class Segmaker:
             def add_site_tags():
                 segment = getseg(segname)
 
-                if 'SLICE_' in site:
+                site_prefix = site.split('_')[0]
+
+                def name_slice():
                     '''
                     Simplify SLICE names like:
                     -SLICE_X12Y102 => SLICE_X0
                     -SLICE_X13Y102 => SLICE_X1
                     '''
                     if re.match(r"SLICE_X[0-9]*[02468]Y", site):
-                        sitekey = "SLICE_X0"
+                        return "SLICE_X0"
                     elif re.match(r"SLICE_X[0-9]*[13579]Y", site):
-                        sitekey = "SLICE_X1"
+                        return "SLICE_X1"
                     else:
                         assert 0
-                else:
-                    assert 0, 'Unhandled site type'
+
+                def name_default():
+                    # most sites are unique within their tile
+                    # TODO: maybe verify against DB?
+                    return site_prefix
+
+                sitekey = {
+                    'slice': name_slice,
+                }.get(site_prefix, name_default)()
 
                 for name, value in self.site_tags[site].items():
                     tags_used.add((site, name))
@@ -223,10 +242,6 @@ class Segmaker:
                     tag = tag.replace(".SLICEL.", ".")
                     segments[segname]["tags"][tag] = value
 
-            # ignore dummy tiles (ex: VBRK)
-            if "bits" not in tiledata:
-                continue
-
             tile_type = tiledata["type"]
             tile_types_found.add(tile_type)
             segments = self.segments_by_type.setdefault(tile_type, dict())
@@ -237,22 +252,31 @@ class Segmaker:
             '''
             tile_type_norm = re.sub("(LL|LM)?_[LR]$", "", tile_type)
 
-            for block_type, bitj in tiledata['bits'].items():
-                # NOTE: multiple tiles may have the same base addr + offset
-                segname = "%s_%03d" % (
-                    # truncate 0x to leave hex string
-                    bitj["baseaddr"][2:],
-                    bitj["offset"])
+            # ignore dummy tiles (ex: VBRK)
+            if len(tiledata['bits']) == 0:
+                continue
+            elif len(tiledata['bits']) == 1:
+                bitj = list(tiledata['bits'].values())[0]
+            else:
+                assert self.def_bt in tiledata[
+                    'bits'], 'Default block not present: %s' % self.def_bt
+                bitj = tiledata['bits'][self.def_bt]
 
-                # process tile name tags
-                if tilename in self.tile_tags:
-                    add_tilename_tags()
+            # NOTE: multiple tiles may have the same base addr + offset
+            segname = "%s_%03d" % (
+                # truncate 0x to leave hex string
+                bitj["baseaddr"][2:],
+                bitj["offset"])
 
-                # process site name tags
-                for site in tiledata["sites"]:
-                    if site not in self.site_tags:
-                        continue
-                    add_site_tags()
+            # process tile name tags
+            if tilename in self.tile_tags:
+                add_tilename_tags()
+
+            # process site name tags
+            for site in tiledata["sites"]:
+                if site not in self.site_tags:
+                    continue
+                add_site_tags()
 
         if self.verbose:
             ntags = recurse_sum(self.site_tags) + recurse_sum(self.tile_tags)
@@ -279,6 +303,7 @@ class Segmaker:
             with open(filename, "w") as f:
                 segments = self.segments_by_type[segtype]
                 for segname, segdata in sorted(segments.items()):
+                    # seg 00020300_010
                     print("seg %s" % segname, file=f)
                     for bitname in sorted(segdata["bits"]):
                         print("bit %s" % bitname, file=f)
diff --git a/prjxray/verilog.py b/prjxray/verilog.py
new file mode 100644
index 00000000..a6175647
--- /dev/null
+++ b/prjxray/verilog.py
@@ -0,0 +1,51 @@
+import sys
+
+
+def top_harness(DIN_N, DOUT_N, f=sys.stdout):
+    f.write(
+        '''
+module top(input clk, stb, di, output do);
+    localparam integer DIN_N = %d;
+    localparam integer DOUT_N = %d;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+
+    roi roi (
+        .clk(clk),
+        .din(din),
+        .dout(dout)
+    );
+endmodule
+''' % (DIN_N, DOUT_N))
+
+
+def instance(mod, name, ports, params={}, sort=True):
+    # TODO: make this print nicer
+    tosort = sorted if sort else lambda x: x
+    print('    %s' % mod)
+    if len(params):
+        print('        #(')
+        for i, (paramk, paramv) in enumerate(tosort(params.items())):
+            comma = '' if i == len(params) - 1 else ','
+            print('            .%s(%s)%s' % (paramk, paramv, comma))
+        print('        )')
+    print('        %s (' % name)
+    for i, (portk, portv) in enumerate(tosort(ports.items())):
+        comma = '' if i == len(ports) - 1 else ','
+        print('            .%s(%s)%s' % (portk, portv, comma))
+    print('        ));')
diff --git a/utils/genheader.sh b/utils/genheader.sh
index 71766634..da35182e 100644
--- a/utils/genheader.sh
+++ b/utils/genheader.sh
@@ -9,7 +9,15 @@ set -ex
 
 # for some reason on sourced script set -e doesn't work
 test $# = 1 || exit 1
-test ! -e "$1"
-mkdir "$1"
-cd "$1"
+test ! -e "$SPECN"
+SPECN=$1
+
+mkdir "$SPECN"
+cd "$SPECN"
+
+export SEED="$(echo $SPECN | md5sum | cut -c1-8)"
+
+function seed_vh () {
+    echo '`define SEED 32'"'h${SEED}" > setseed.vh
+}
 
diff --git a/utils/mergedb.sh b/utils/mergedb.sh
index 94014ac8..391d3e40 100644
--- a/utils/mergedb.sh
+++ b/utils/mergedb.sh
@@ -1,5 +1,8 @@
 #!/bin/bash
 
+# $1: DB type
+# $2: filename to merge in
+
 set -ex
 test $# = 2
 test -e "$2"
@@ -9,6 +12,10 @@ tmp2=`mktemp -p .`
 
 db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/segbits_$1.db
 
+# Fuzzers verify L/R data is equivilent
+# However, expand back to L/R to make downstream tools not depend on this
+# in case we later find exceptions
+
 case "$1" in
 	clbll_l)
 		sed < "$2" > "$tmp1" \
@@ -37,6 +44,11 @@ case "$1" in
 	bram_r)
 		sed < "$2" > "$tmp1" -e 's/^BRAM\./BRAM_R./' ;;
 
+	bram_l.block_ram)
+		sed < "$2" > "$tmp1" -e 's/^BRAM\./BRAM_L./' ;;
+	bram_r.block_ram)
+		sed < "$2" > "$tmp1" -e 's/^BRAM\./BRAM_R./' ;;
+
 	int_l)
 		sed < "$2" > "$tmp1" -e 's/^INT\./INT_L./' ;;
 	int_r)