From 5f6d9ff84ea9a2a6ad78a54e3bcc3c98e550ef7b Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 15 May 2020 22:35:36 -0700 Subject: [PATCH 1/3] Fix bad setting of XRAY_IOI3_TILES for 100t part. Signed-off-by: Tim Callahan --- settings/artix7_100t.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/settings/artix7_100t.sh b/settings/artix7_100t.sh index a89c214d..0c4fc1a7 100644 --- a/settings/artix7_100t.sh +++ b/settings/artix7_100t.sh @@ -8,7 +8,7 @@ export XRAY_ROI_TILEGRID="RAMB36_X0Y0:RAMB36_X3Y39 RAMB18_X0Y0:RAMB18_X3Y79 DSP4 export XRAY_EXCLUDE_ROI_TILEGRID="" -export XRAY_IOI3_TILES="RIOI3_X57Y101 LIOI3_X0Y101" +export XRAY_IOI3_TILES="RIOI3_X57Y109 LIOI3_X0Y109" # clock pin export XRAY_PIN_00="Y22" From 98a6bf3071226050338d32989429add53793d1b5 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 15 May 2020 22:36:45 -0700 Subject: [PATCH 2/3] Make Makefile more robust by sourcing settings/artix7.sh when needed. Signed-off-by: Tim Callahan --- Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9e1082ce..396e93f5 100644 --- a/Makefile +++ b/Makefile @@ -177,8 +177,10 @@ $(foreach PART,$(XRAY_PARTS),$(eval $(call multiple-parts,$(PART)))) db-extras-artix7-parts: $(addprefix db-part-only-,$(ARTIX_PARTS)) db-extras-artix7-harness: - +XRAY_PIN_00=J13 XRAY_PIN_01=J14 XRAY_PIN_02=K15 XRAY_PIN_03=K16 \ - XRAY_PART=xc7a35tftg256-1 XRAY_EQUIV_PART=xc7a50tfgg484-1 $(MAKE) -C fuzzers roi_only + +source settings/artix7.sh && \ + XRAY_PIN_00=J13 XRAY_PIN_01=J14 XRAY_PIN_02=K15 XRAY_PIN_03=K16 \ + XRAY_PART=xc7a35tftg256-1 XRAY_EQUIV_PART=xc7a50tfgg484-1 \ + $(MAKE) -C fuzzers roi_only +source settings/artix7_100t.sh && \ XRAY_PIN_00=N15 XRAY_PART=xc7a100tcsg324-1 XRAY_EQUIV_PART=xc7a100tfgg676-1 \ $(MAKE) -C fuzzers roi_only From 9d0499f87a2ae5fff68dfce85183a7d35642ac23 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Mon, 18 May 2020 13:14:58 -0700 Subject: [PATCH 3/3] Update settings/artix7*.sh with helpful comments regarding XRAY_IOI3_TILES and other non-obvious things. Signed-off-by: Tim Callahan --- Makefile | 5 +++++ settings/artix7.sh | 6 ++++++ settings/artix7_100t.sh | 4 ++++ settings/artix7_200t.sh | 6 ++++++ 4 files changed, 21 insertions(+) diff --git a/Makefile b/Makefile index 396e93f5..ecc11881 100644 --- a/Makefile +++ b/Makefile @@ -176,6 +176,11 @@ $(foreach PART,$(XRAY_PARTS),$(eval $(call multiple-parts,$(PART)))) db-extras-artix7-parts: $(addprefix db-part-only-,$(ARTIX_PARTS)) +# This explicitly sources each settings script as needed so that +# you don't need to worry about manually sourcing the right script before making. +# Some of these commands handle additional parts/packages that are *not* fully bonded. +# For any pin defined in settings/*.sh that is *not* bonded in this part/package, +# override the XRAY_PIN_0X setting below to pick a pin that *is* bonded. db-extras-artix7-harness: +source settings/artix7.sh && \ XRAY_PIN_00=J13 XRAY_PIN_01=J14 XRAY_PIN_02=K15 XRAY_PIN_03=K16 \ diff --git a/settings/artix7.sh b/settings/artix7.sh index 805cee9f..22658216 100644 --- a/settings/artix7.sh +++ b/settings/artix7.sh @@ -8,6 +8,10 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAM export XRAY_EXCLUDE_ROI_TILEGRID="" +# This is used by fuzzers/005-tilegrid/generate_full.py +# (special handling for frame addresses of certain IOIs -- see the script for details). +# This needs to be changed for any new device! +# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST. export XRAY_IOI3_TILES="LIOI3_X0Y9 RIOI3_X43Y9" # These settings must remain in sync @@ -19,7 +23,9 @@ export XRAY_ROI_GRID_X2="58" export XRAY_ROI_GRID_Y1="0" export XRAY_ROI_GRID_Y2="51" +# clock pin export XRAY_PIN_00="E22" +# data pins export XRAY_PIN_01="D22" export XRAY_PIN_02="E21" export XRAY_PIN_03="D21" diff --git a/settings/artix7_100t.sh b/settings/artix7_100t.sh index 0c4fc1a7..919b0d6f 100644 --- a/settings/artix7_100t.sh +++ b/settings/artix7_100t.sh @@ -8,6 +8,10 @@ export XRAY_ROI_TILEGRID="RAMB36_X0Y0:RAMB36_X3Y39 RAMB18_X0Y0:RAMB18_X3Y79 DSP4 export XRAY_EXCLUDE_ROI_TILEGRID="" +# This is used by fuzzers/005-tilegrid/generate_full.py +# (special handling for frame addresses of certain IOIs -- see the script for details). +# This needs to be changed for any new device! +# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST. export XRAY_IOI3_TILES="RIOI3_X57Y109 LIOI3_X0Y109" # clock pin diff --git a/settings/artix7_200t.sh b/settings/artix7_200t.sh index 1f5bbe23..e069dc6e 100644 --- a/settings/artix7_200t.sh +++ b/settings/artix7_200t.sh @@ -8,9 +8,15 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X163Y249 RAMB18_X0Y0:RAMB18_X8Y99 RAM export XRAY_EXCLUDE_ROI_TILEGRID="" +# This is used by fuzzers/005-tilegrid/generate_full.py +# (special handling for frame addresses of certain IOIs -- see the script for details). +# This needs to be changed for any new device! +# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST. export XRAY_IOI3_TILES="RIOI3_X105Y9 LIOI3_X0Y9" +# clock pin export XRAY_PIN_00="R26" +# data pins export XRAY_PIN_01="P26" export XRAY_PIN_02="N26" export XRAY_PIN_03="M27"