From 57a7da706c8cbb7eff8140d7624c9f1171ec621d Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Mon, 18 Jan 2021 17:17:51 +0100 Subject: [PATCH 1/5] minitest: add lite-sata minitest to verify GTP status Signed-off-by: Alessandro Comodi --- minitests/litex/nexys_video_sata/.gitignore | 6 ++ minitests/litex/nexys_video_sata/Makefile | 58 +++++++++++++++++++ .../litex/nexys_video_sata/requirements.txt | 21 +++++++ minitests/litex/nexys_video_sata/retarget.v | 8 +++ minitests/litex/nexys_video_sata/tcl/par.tcl | 24 ++++++++ minitests/litex/nexys_video_sata/tcl/syn.tcl | 18 ++++++ 6 files changed, 135 insertions(+) create mode 100644 minitests/litex/nexys_video_sata/.gitignore create mode 100644 minitests/litex/nexys_video_sata/Makefile create mode 100644 minitests/litex/nexys_video_sata/requirements.txt create mode 100644 minitests/litex/nexys_video_sata/retarget.v create mode 100644 minitests/litex/nexys_video_sata/tcl/par.tcl create mode 100644 minitests/litex/nexys_video_sata/tcl/syn.tcl diff --git a/minitests/litex/nexys_video_sata/.gitignore b/minitests/litex/nexys_video_sata/.gitignore new file mode 100644 index 00000000..79e02def --- /dev/null +++ b/minitests/litex/nexys_video_sata/.gitignore @@ -0,0 +1,6 @@ +# Python data +src + +# Build data +build* +sata.* diff --git a/minitests/litex/nexys_video_sata/Makefile b/minitests/litex/nexys_video_sata/Makefile new file mode 100644 index 00000000..54d7f575 --- /dev/null +++ b/minitests/litex/nexys_video_sata/Makefile @@ -0,0 +1,58 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC + +SHELL = bash + +SYNTH ?= vivado +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +PART = xc7a200tsbg484-1 +PROJECT_NAME = sata + +clean: + @find . -name "build-par.*" | xargs rm -rf + @find . -name "build-syn.*" | xargs rm -rf + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.log + @rm -f *.dcp + +help: + @echo "Usage: make all [SYNTH=]" + +.PHONY: clean help + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +build.ok: + ./src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 + touch build/build.ok + +VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \ + ./src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v + +ifeq ($(SYNTH), yosys) +$(PROJECT_NAME).edif: $(YOSYS) build/build.ok + $(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log + +else ifeq ($(SYNTH), vivado) +$(PROJECT_NAME).edif: build/build.ok tcl/syn.tcl + mkdir -p build-syn.$(basename $@) + cd build-syn.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +endif + +$(PROJECT_NAME).bit: $(PROJECT_NAME).edif tcl/par.tcl + mkdir -p build-par.$(basename $@) + cd build-par.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +$(PROJECT_NAME).fasm: $(PROJECT_NAME).bit + source $(XRAY_DIR)/settings/artix7_200t.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose $(PROJECT_NAME).bit > $(PROJECT_NAME).fasm diff --git a/minitests/litex/nexys_video_sata/requirements.txt b/minitests/litex/nexys_video_sata/requirements.txt new file mode 100644 index 00000000..6341fb5d --- /dev/null +++ b/minitests/litex/nexys_video_sata/requirements.txt @@ -0,0 +1,21 @@ +# Litex +-e git+https://github.com/enjoy-digital/litex#egg=litex +-e git+https://github.com/enjoy-digital/litedram#egg=litedram +-e git+https://github.com/enjoy-digital/liteeth#egg=liteeth +-e git+https://github.com/enjoy-digital/liteiclink#egg=liteiclink +-e git+https://github.com/enjoy-digital/litejesd204b#egg=litejesd204b +-e git+https://github.com/enjoy-digital/litepcie#egg=litepcie +-e git+https://github.com/enjoy-digital/litesata#egg=litesata +-e git+https://github.com/enjoy-digital/litescope#egg=litescope +-e git+https://github.com/enjoy-digital/litesdcard#egg=litesdcard +-e git+https://github.com/enjoy-digital/litevideo#egg=litevideo +-e git+https://github.com/litex-hub/litehyperbus#egg=litehyperbus +-e git+https://github.com/litex-hub/litespi#egg=litespi +-e git+https://github.com/litex-hub/litex-boards#egg=litex_boards + +# Migen and nMigen +-e git+https://github.com/m-labs/migen#egg=migen +-e git+https://github.com/nmigen/nmigen#egg=nmigen + + +-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv#egg=pythondata_cpu_vexriscv diff --git a/minitests/litex/nexys_video_sata/retarget.v b/minitests/litex/nexys_video_sata/retarget.v new file mode 100644 index 00000000..c625c1bc --- /dev/null +++ b/minitests/litex/nexys_video_sata/retarget.v @@ -0,0 +1,8 @@ +module FD (output reg Q, input C, D); + +parameter [0:0] INIT = 1'b0; + +FDRE #(.INIT(INIT)) __TECHMAP_REPLACE__ (.Q(Q), .C(C), .D(D), .CE(1'b1), .R(1'b0)); + +endmodule + diff --git a/minitests/litex/nexys_video_sata/tcl/par.tcl b/minitests/litex/nexys_video_sata/tcl/par.tcl new file mode 100644 index 00000000..9412af43 --- /dev/null +++ b/minitests/litex/nexys_video_sata/tcl/par.tcl @@ -0,0 +1,24 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -name $env(PROJECT_NAME) -part $env(PART) + +read_edif ../$env(PROJECT_NAME).edif + +link_design -part $env(PART) +source ../build/nexys_video/gateware/nexys_video.xdc + +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] +set_property SEVERITY {Warning} [get_drc_checks REQP-1936] + +place_design +route_design + +write_checkpoint -force ../$env(PROJECT_NAME).dcp + +write_bitstream -force ../$env(PROJECT_NAME).bit diff --git a/minitests/litex/nexys_video_sata/tcl/syn.tcl b/minitests/litex/nexys_video_sata/tcl/syn.tcl new file mode 100644 index 00000000..0e3652fa --- /dev/null +++ b/minitests/litex/nexys_video_sata/tcl/syn.tcl @@ -0,0 +1,18 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -name $env(PROJECT_NAME) -part $env(XRAY_PART) + +read_verilog ../build/nexys_video/gateware/nexys_video.v ../src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v + +synth_design -top nexys_video -max_dsp 0 + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +write_edif -force ../$env(PROJECT_NAME).edif From 8210db1aa577d94668ce21d1a630efc39f8506ed Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Mon, 18 Jan 2021 17:48:05 +0100 Subject: [PATCH 2/5] minitest: litex: litesata: add make target to get litex Signed-off-by: Alessandro Comodi --- minitests/litex/nexys_video_sata/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/minitests/litex/nexys_video_sata/Makefile b/minitests/litex/nexys_video_sata/Makefile index 54d7f575..a4de56fb 100644 --- a/minitests/litex/nexys_video_sata/Makefile +++ b/minitests/litex/nexys_video_sata/Makefile @@ -30,7 +30,11 @@ help: $(YOSYS): cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) -build.ok: +litex-install.ok: + pip install -r requirements.txt + touch litex-install.ok + +build/build.ok: litex-install.ok ./src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 touch build/build.ok From f5dfb69d19b7e2a51d3e1c93fa93433e8c90208c Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Fri, 22 Jan 2021 13:40:35 +0100 Subject: [PATCH 3/5] minitest: litex: litesata: fix Makefile and build process Signed-off-by: Alessandro Comodi --- minitests/litex/nexys_video_sata/.gitignore | 1 + minitests/litex/nexys_video_sata/Makefile | 16 ++++++++---- .../litex/nexys_video_sata/requirements.txt | 25 +++++++------------ minitests/litex/nexys_video_sata/tcl/syn.tcl | 2 +- 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/minitests/litex/nexys_video_sata/.gitignore b/minitests/litex/nexys_video_sata/.gitignore index 79e02def..bb383ef0 100644 --- a/minitests/litex/nexys_video_sata/.gitignore +++ b/minitests/litex/nexys_video_sata/.gitignore @@ -4,3 +4,4 @@ src # Build data build* sata.* +*.ok diff --git a/minitests/litex/nexys_video_sata/Makefile b/minitests/litex/nexys_video_sata/Makefile index a4de56fb..7bbb5630 100644 --- a/minitests/litex/nexys_video_sata/Makefile +++ b/minitests/litex/nexys_video_sata/Makefile @@ -13,14 +13,20 @@ YOSYS = $(XRAY_DIR)/third_party/yosys/yosys PART = xc7a200tsbg484-1 PROJECT_NAME = sata +all: $(PROJECT_NAME).fasm + clean: - @find . -name "build-par.*" | xargs rm -rf - @find . -name "build-syn.*" | xargs rm -rf + @rm -rf build* @rm -f *.edif @rm -f *.bit @rm -f *.bin @rm -f *.log @rm -f *.dcp + @rm -f *.fasm + +clean_litex: + @rm -rf ${VIRTUAL_ENV}/src + @rm -f litex-install.ok help: @echo "Usage: make all [SYNTH=]" @@ -35,15 +41,15 @@ litex-install.ok: touch litex-install.ok build/build.ok: litex-install.ok - ./src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 + ${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 touch build/build.ok VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \ - ./src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v + ${VIRTUAL_ENV}/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v ifeq ($(SYNTH), yosys) $(PROJECT_NAME).edif: $(YOSYS) build/build.ok - $(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log + $(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl -nodsp; write_edif -pvector bra -attrprop $@" -l $@.log else ifeq ($(SYNTH), vivado) $(PROJECT_NAME).edif: build/build.ok tcl/syn.tcl diff --git a/minitests/litex/nexys_video_sata/requirements.txt b/minitests/litex/nexys_video_sata/requirements.txt index 6341fb5d..159c8825 100644 --- a/minitests/litex/nexys_video_sata/requirements.txt +++ b/minitests/litex/nexys_video_sata/requirements.txt @@ -1,21 +1,14 @@ # Litex --e git+https://github.com/enjoy-digital/litex#egg=litex --e git+https://github.com/enjoy-digital/litedram#egg=litedram --e git+https://github.com/enjoy-digital/liteeth#egg=liteeth --e git+https://github.com/enjoy-digital/liteiclink#egg=liteiclink --e git+https://github.com/enjoy-digital/litejesd204b#egg=litejesd204b --e git+https://github.com/enjoy-digital/litepcie#egg=litepcie --e git+https://github.com/enjoy-digital/litesata#egg=litesata --e git+https://github.com/enjoy-digital/litescope#egg=litescope --e git+https://github.com/enjoy-digital/litesdcard#egg=litesdcard --e git+https://github.com/enjoy-digital/litevideo#egg=litevideo --e git+https://github.com/litex-hub/litehyperbus#egg=litehyperbus --e git+https://github.com/litex-hub/litespi#egg=litespi --e git+https://github.com/litex-hub/litex-boards#egg=litex_boards +-e git+https://github.com/enjoy-digital/litex@e8cfe3b6ea4d8fbea0080d5cae4302169fc804cb#egg=litex +-e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram +-e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth +-e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink +-e git+https://github.com/enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7#egg=litesata +-e git+https://github.com/litex-hub/litex-boards@bee71da7746c6fda0d4e1942452510e11f06c14a#egg=litex_boards # Migen and nMigen --e git+https://github.com/m-labs/migen#egg=migen --e git+https://github.com/nmigen/nmigen#egg=nmigen +-e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen +-e git+https://github.com/nmigen/nmigen@490fca57457b16421f7b3f2c7812bb229b17744a#egg=nmigen --e git+https://github.com/litex-hub/pythondata-cpu-vexriscv#egg=pythondata_cpu_vexriscv +-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv diff --git a/minitests/litex/nexys_video_sata/tcl/syn.tcl b/minitests/litex/nexys_video_sata/tcl/syn.tcl index 0e3652fa..7299419d 100644 --- a/minitests/litex/nexys_video_sata/tcl/syn.tcl +++ b/minitests/litex/nexys_video_sata/tcl/syn.tcl @@ -7,7 +7,7 @@ # SPDX-License-Identifier: ISC create_project -force -name $env(PROJECT_NAME) -part $env(XRAY_PART) -read_verilog ../build/nexys_video/gateware/nexys_video.v ../src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v +read_verilog ../build/nexys_video/gateware/nexys_video.v $env(VIRTUAL_ENV)/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v synth_design -top nexys_video -max_dsp 0 From 730a6518d4f127341322334f1d6d1a12237fd8ab Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Fri, 22 Jan 2021 13:41:29 +0100 Subject: [PATCH 4/5] minitest: litex: litesata: add README Signed-off-by: Alessandro Comodi --- minitests/litex/nexys_video_sata/README.md | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 minitests/litex/nexys_video_sata/README.md diff --git a/minitests/litex/nexys_video_sata/README.md b/minitests/litex/nexys_video_sata/README.md new file mode 100644 index 00000000..89dc56c3 --- /dev/null +++ b/minitests/litex/nexys_video_sata/README.md @@ -0,0 +1,29 @@ +LiteSATA minitest +================= + +This minitest is intended to provide a counter-prove on the possible remaining features to document for +the Gigabit Transcievers (GTP tiles). + +It uses the following litex modules: + +| Repo URL | SHA | +| --------------------------------------------------------- | ------- | +| | 8cfe3b6 | +| | ab2423e | +| | 7448170 | +| | 0980a7c | +| | fae9f8d | +| | bee71da | +| | 40b1092 | +| | 490fca5 | +| | 16c5dde | + +The minitest synthesis step can be performed with Yosys or Vivado. + +The final FASM file with the `unknown bits` can be obtained by running the following: + +```bash +make all +``` + +All the pre-requisites (LiteX, Yosys, etc.) are automatically installed/built. It is required though to have Vivado installed in the system. From ea5879af183568c21319a1b51a8c8628a131d5e1 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Fri, 22 Jan 2021 16:52:20 +0100 Subject: [PATCH 5/5] minitest: litex: litesata: download riscv-gcc as well in Makefile Signed-off-by: Alessandro Comodi --- minitests/litex/nexys_video_sata/Makefile | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/minitests/litex/nexys_video_sata/Makefile b/minitests/litex/nexys_video_sata/Makefile index 7bbb5630..9a0cedbf 100644 --- a/minitests/litex/nexys_video_sata/Makefile +++ b/minitests/litex/nexys_video_sata/Makefile @@ -12,6 +12,7 @@ SYNTH ?= vivado YOSYS = $(XRAY_DIR)/third_party/yosys/yosys PART = xc7a200tsbg484-1 PROJECT_NAME = sata +RISCV_DIR = riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14 all: $(PROJECT_NAME).fasm @@ -28,6 +29,10 @@ clean_litex: @rm -rf ${VIRTUAL_ENV}/src @rm -f litex-install.ok +clean_riscv: + @rm -rf $(RISCV_DIR) + @rm -f riscv-gcc.ok + help: @echo "Usage: make all [SYNTH=]" @@ -40,8 +45,12 @@ litex-install.ok: pip install -r requirements.txt touch litex-install.ok -build/build.ok: litex-install.ok - ${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 +riscv-gcc.ok: + wget -qO- https://static.dev.sifive.com/dev-tools/$(RISCV_DIR).tar.gz | tar -xz + touch riscv-gcc.ok + +build/build.ok: litex-install.ok riscv-gcc.ok + env PATH=${PATH}:${PWD}/${RISCV_DIR}/bin ${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 touch build/build.ok VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \