diff --git a/minitests/litex/nexys_video_sata/.gitignore b/minitests/litex/nexys_video_sata/.gitignore new file mode 100644 index 00000000..bb383ef0 --- /dev/null +++ b/minitests/litex/nexys_video_sata/.gitignore @@ -0,0 +1,7 @@ +# Python data +src + +# Build data +build* +sata.* +*.ok diff --git a/minitests/litex/nexys_video_sata/Makefile b/minitests/litex/nexys_video_sata/Makefile new file mode 100644 index 00000000..9a0cedbf --- /dev/null +++ b/minitests/litex/nexys_video_sata/Makefile @@ -0,0 +1,77 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC + +SHELL = bash + +SYNTH ?= vivado +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +PART = xc7a200tsbg484-1 +PROJECT_NAME = sata +RISCV_DIR = riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14 + +all: $(PROJECT_NAME).fasm + +clean: + @rm -rf build* + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.log + @rm -f *.dcp + @rm -f *.fasm + +clean_litex: + @rm -rf ${VIRTUAL_ENV}/src + @rm -f litex-install.ok + +clean_riscv: + @rm -rf $(RISCV_DIR) + @rm -f riscv-gcc.ok + +help: + @echo "Usage: make all [SYNTH=]" + +.PHONY: clean help + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +litex-install.ok: + pip install -r requirements.txt + touch litex-install.ok + +riscv-gcc.ok: + wget -qO- https://static.dev.sifive.com/dev-tools/$(RISCV_DIR).tar.gz | tar -xz + touch riscv-gcc.ok + +build/build.ok: litex-install.ok riscv-gcc.ok + env PATH=${PATH}:${PWD}/${RISCV_DIR}/bin ${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000 + touch build/build.ok + +VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \ + ${VIRTUAL_ENV}/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v + +ifeq ($(SYNTH), yosys) +$(PROJECT_NAME).edif: $(YOSYS) build/build.ok + $(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl -nodsp; write_edif -pvector bra -attrprop $@" -l $@.log + +else ifeq ($(SYNTH), vivado) +$(PROJECT_NAME).edif: build/build.ok tcl/syn.tcl + mkdir -p build-syn.$(basename $@) + cd build-syn.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +endif + +$(PROJECT_NAME).bit: $(PROJECT_NAME).edif tcl/par.tcl + mkdir -p build-par.$(basename $@) + cd build-par.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +$(PROJECT_NAME).fasm: $(PROJECT_NAME).bit + source $(XRAY_DIR)/settings/artix7_200t.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose $(PROJECT_NAME).bit > $(PROJECT_NAME).fasm diff --git a/minitests/litex/nexys_video_sata/README.md b/minitests/litex/nexys_video_sata/README.md new file mode 100644 index 00000000..89dc56c3 --- /dev/null +++ b/minitests/litex/nexys_video_sata/README.md @@ -0,0 +1,29 @@ +LiteSATA minitest +================= + +This minitest is intended to provide a counter-prove on the possible remaining features to document for +the Gigabit Transcievers (GTP tiles). + +It uses the following litex modules: + +| Repo URL | SHA | +| --------------------------------------------------------- | ------- | +| | 8cfe3b6 | +| | ab2423e | +| | 7448170 | +| | 0980a7c | +| | fae9f8d | +| | bee71da | +| | 40b1092 | +| | 490fca5 | +| | 16c5dde | + +The minitest synthesis step can be performed with Yosys or Vivado. + +The final FASM file with the `unknown bits` can be obtained by running the following: + +```bash +make all +``` + +All the pre-requisites (LiteX, Yosys, etc.) are automatically installed/built. It is required though to have Vivado installed in the system. diff --git a/minitests/litex/nexys_video_sata/requirements.txt b/minitests/litex/nexys_video_sata/requirements.txt new file mode 100644 index 00000000..159c8825 --- /dev/null +++ b/minitests/litex/nexys_video_sata/requirements.txt @@ -0,0 +1,14 @@ +# Litex +-e git+https://github.com/enjoy-digital/litex@e8cfe3b6ea4d8fbea0080d5cae4302169fc804cb#egg=litex +-e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram +-e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth +-e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink +-e git+https://github.com/enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7#egg=litesata +-e git+https://github.com/litex-hub/litex-boards@bee71da7746c6fda0d4e1942452510e11f06c14a#egg=litex_boards + +# Migen and nMigen +-e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen +-e git+https://github.com/nmigen/nmigen@490fca57457b16421f7b3f2c7812bb229b17744a#egg=nmigen + + +-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv diff --git a/minitests/litex/nexys_video_sata/retarget.v b/minitests/litex/nexys_video_sata/retarget.v new file mode 100644 index 00000000..c625c1bc --- /dev/null +++ b/minitests/litex/nexys_video_sata/retarget.v @@ -0,0 +1,8 @@ +module FD (output reg Q, input C, D); + +parameter [0:0] INIT = 1'b0; + +FDRE #(.INIT(INIT)) __TECHMAP_REPLACE__ (.Q(Q), .C(C), .D(D), .CE(1'b1), .R(1'b0)); + +endmodule + diff --git a/minitests/litex/nexys_video_sata/tcl/par.tcl b/minitests/litex/nexys_video_sata/tcl/par.tcl new file mode 100644 index 00000000..9412af43 --- /dev/null +++ b/minitests/litex/nexys_video_sata/tcl/par.tcl @@ -0,0 +1,24 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -name $env(PROJECT_NAME) -part $env(PART) + +read_edif ../$env(PROJECT_NAME).edif + +link_design -part $env(PART) +source ../build/nexys_video/gateware/nexys_video.xdc + +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] +set_property SEVERITY {Warning} [get_drc_checks REQP-1936] + +place_design +route_design + +write_checkpoint -force ../$env(PROJECT_NAME).dcp + +write_bitstream -force ../$env(PROJECT_NAME).bit diff --git a/minitests/litex/nexys_video_sata/tcl/syn.tcl b/minitests/litex/nexys_video_sata/tcl/syn.tcl new file mode 100644 index 00000000..7299419d --- /dev/null +++ b/minitests/litex/nexys_video_sata/tcl/syn.tcl @@ -0,0 +1,18 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -name $env(PROJECT_NAME) -part $env(XRAY_PART) + +read_verilog ../build/nexys_video/gateware/nexys_video.v $env(VIRTUAL_ENV)/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v + +synth_design -top nexys_video -max_dsp 0 + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +write_edif -force ../$env(PROJECT_NAME).edif