From a27486271ca8c5025479393681e8a6c1c4596721 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 15 Oct 2018 15:53:51 -0700 Subject: [PATCH] bram minitest: clean up makefile Signed-off-by: John McMaster --- minitests/bram_basic/Makefile | 37 +++------ minitests/bram_basic/diff.mk | 11 +++ minitests/bram_basic/top.v | 143 +++++++++++++++++++++------------- 3 files changed, 109 insertions(+), 82 deletions(-) create mode 100644 minitests/bram_basic/diff.mk diff --git a/minitests/bram_basic/Makefile b/minitests/bram_basic/Makefile index 7a1166c7..8fc8f2c9 100644 --- a/minitests/bram_basic/Makefile +++ b/minitests/bram_basic/Makefile @@ -1,38 +1,21 @@ -all: build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff +all: build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff clean: rm -rf build +# Toggle one bit to locate where first BRAM data is +build/roi_bramd_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bit01.diff PRJL=roi_bramd_bit0 PRJR=roi_bramd_bit1 # Toggle all bits in a single BRAM data section -build/roi_bramd_bits01.diff: build/roi_bramd_bits0/design.bits build/roi_bramd_bits1/design.bits - diff build/roi_bramd_bits{0,1}/design.bits >build/roi_bramd_bits01.diff || true - -build/roi_bramd_bits0/design.bits: - PROJECT=roi_bramd_bits0 bash runme.sh - -build/roi_bramd_bits1/design.bits: - PROJECT=roi_bramd_bits1 bash runme.sh - +build/roi_bramd_bits01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bits01.diff PRJL=roi_bramd_bits0 PRJR=roi_bramd_bits1 # Toggle one bit in each BRAM data section -build/roi_bramds_bit01.diff: build/roi_bramds_bit0/design.bits build/roi_bramds_bit1/design.bits - diff build/roi_bramds_bit{0,1}/design.bits >build/roi_bramds_bit01.diff || true - -build/roi_bramds_bit0/design.bits: - PROJECT=roi_bramds_bit0 bash runme.sh - -build/roi_bramds_bit1/design.bits: - PROJECT=roi_bramds_bit1 bash runme.sh - +build/roi_bramds_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramds_bit01.diff PRJL=roi_bramds_bit0 PRJR=roi_bramds_bit1 # Toggle one bit in each BRAM config section -build/roi_bramis_bit01.diff: build/roi_bramis_bit0/design.bits build/roi_bramis_bit1/design.bits - diff build/roi_bramis_bit{0,1}/design.bits >build/roi_bramis_bit01.diff || true - -build/roi_bramis_bit0/design.bits: - PROJECT=roi_bramis_bit0 bash runme.sh - -build/roi_bramis_bit1/design.bits: - PROJECT=roi_bramis_bit1 bash runme.sh +build/roi_bramis_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramis_bit01.diff PRJL=roi_bramis_bit0 PRJR=roi_bramis_bit1 diff --git a/minitests/bram_basic/diff.mk b/minitests/bram_basic/diff.mk new file mode 100644 index 00000000..b2c2ff60 --- /dev/null +++ b/minitests/bram_basic/diff.mk @@ -0,0 +1,11 @@ +all: $(OUT_DIFF) + +$(OUT_DIFF): build/$(PRJL)/design.bits build/$(PRJR)/design.bits + diff build/$(PRJL)/design.bits build/$(PRJR)/design.bits >$(OUT_DIFF) || true + +build/$(PRJL)/design.bits: + PROJECT=$(PRJL) bash runme.sh + +build/$(PRJR)/design.bits: + PROJECT=$(PRJR) bash runme.sh + diff --git a/minitests/bram_basic/top.v b/minitests/bram_basic/top.v index 69a934f6..62350d8c 100644 --- a/minitests/bram_basic/top.v +++ b/minitests/bram_basic/top.v @@ -46,74 +46,86 @@ DATA ROI Toggle a single data bit to locate a single instance ******************************************************************************/ module roi_bramd_bit0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule module roi_bramd_bit1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bram18d_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bram18d_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule /****************************************************************************** Toggle all bits to show the size of the data section ******************************************************************************/ + module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule /****************************************************************************** Toggle all the data bits in the ROI to show pitch between entries ******************************************************************************/ + module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}})) r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}})) r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}})) r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}})) r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}})) r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}})) r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}})) r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}})) r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}})) r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); endmodule module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b1), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b1), .INIT({256{1'b0}})) r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b1), .INIT({256{1'b0}})) r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b1), .INIT({256{1'b0}})) r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b1), .INIT({256{1'b0}})) r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b1), .INIT({256{1'b0}})) r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b1), .INIT({256{1'b0}})) r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b1), .INIT({256{1'b0}})) r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b1), .INIT({256{1'b0}})) r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b1), .INIT({256{1'b0}})) + ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b1), .INIT({256{1'b0}})) r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); endmodule @@ -121,6 +133,56 @@ endmodule CONFIG ROI ******************************************************************************/ +module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0)) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +module roi_bramis_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y10"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y11"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y12"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y13"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y14"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y15"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y16"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y17"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y18"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y19"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +/****************************************************************************** +Misc ROI +******************************************************************************/ + //ram_RAMB36E1 too much churn to be useful to compare vs above //instead lets change something more subtle // ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND: roi/r0/ram programming @@ -145,32 +207,6 @@ module roi_bram36_1s(input clk, input [255:0] din, output [255:0] dout); r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule -/* -One BRAM per tile -*/ -module roi_brams(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b1), .INIT({256{1'b0}})) - r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b1), .INIT({256{1'b0}})) - r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b1), .INIT({256{1'b0}})) - r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b1), .INIT({256{1'b0}})) - r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b1), .INIT({256{1'b0}})) - r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b1), .INIT({256{1'b0}})) - r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b1), .INIT({256{1'b0}})) - r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b1), .INIT({256{1'b0}})) - r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b1), .INIT({256{1'b0}})) - r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); -endmodule - /* Place everything into first tile This is invalid since 18/36 share resources @@ -184,10 +220,6 @@ module roi_invalid(input clk, input [255:0] din, output [255:0] dout); r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); endmodule -/****************************************************************************** -Misc ROI -******************************************************************************/ - //HCK test //XXX: what specifically was this testing? module roi_hck(input clk, input [255:0] din, output [255:0] dout); @@ -341,6 +373,7 @@ module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter IS_ENARDEN_INVERTED = 1'b0; RAMB36E1 #( .INITP_00(INIT), @@ -492,7 +525,7 @@ module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout); .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0),