diff --git a/fuzzers/025-bram-config/bits.dbf b/fuzzers/025-bram-config/bits.dbf index ac18652f..5a2605a2 100644 --- a/fuzzers/025-bram-config/bits.dbf +++ b/fuzzers/025-bram-config/bits.dbf @@ -3,10 +3,16 @@ 27_43 27_44 27_45,BRAM.RAMB18_Y0.READ_WIDTH_B_1 27_51 27_52 27_53,BRAM.RAMB18_Y0.WRITE_WIDTH_A_1 27_59 27_60 27_61,BRAM.RAMB18_Y0.WRITE_WIDTH_B_1 +27_96,BRAM.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE +27_124,BRAM.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG +27_125,BRAM.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG # Y1 27_285 27_284 27_283,BRAM.RAMB18_Y1.READ_WIDTH_A_1 27_277 27_276 27_275,BRAM.RAMB18_Y1.READ_WIDTH_B_1 27_269 27_268 27_267,BRAM.RAMB18_Y1.WRITE_WIDTH_A_1 27_261 27_260 27_259,BRAM.RAMB18_Y1.WRITE_WIDTH_B_1 +27_224,BRAM.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE +27_196,BRAM.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG +27_195,BRAM.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG diff --git a/fuzzers/025-bram-config/generate.py b/fuzzers/025-bram-config/generate.py index b9a0a127..34802ad8 100644 --- a/fuzzers/025-bram-config/generate.py +++ b/fuzzers/025-bram-config/generate.py @@ -98,6 +98,18 @@ def write_mode_tags(segmk, ps, site): segmk.add_site_tag( site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE") +def write_rstreg_priority(segmk, ps, site): + for param in ["RSTREG_PRIORITY_A", "RSTREG_PRIORITY_B"]: + set_val = verilog.unquote(ps[param]) + for opt in ["RSTREG", "REGCE"]: + segmk.add_site_tag(site, "{}_{}".format(param, opt), + set_val == opt) + +def write_rdaddr_collision(segmk, ps, site): + for opt in ["DELAYED_WRITE", "PERFORMANCE"]: + set_val = verilog.unquote(ps['RDADDR_COLLISION_HWCONFIG']) + segmk.add_site_tag(site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt), + set_val == opt) def run(): @@ -121,6 +133,8 @@ def run(): bus_tags(segmk, ps, site) rw_width_tags(segmk, ps, site) write_mode_tags(segmk, ps, site) + write_rstreg_priority(segmk, ps, site) + write_rdaddr_collision(segmk, ps, site) def bitfilter(frame, bit): # rw_width_tags() aliasing interconnect on large widths diff --git a/fuzzers/025-bram-config/top.py b/fuzzers/025-bram-config/top.py index 2f0babbb..3a1cba28 100644 --- a/fuzzers/025-bram-config/top.py +++ b/fuzzers/025-bram-config/top.py @@ -36,256 +36,182 @@ def gen_brams(): yield ('RAMB18E1', site) -brams = list(gen_brams()) -DUTN = len(brams) -DIN_N = DUTN * 8 -DOUT_N = DUTN * 8 +def main(): + brams = list(gen_brams()) + DUTN = len(brams) + DIN_N = DUTN * 8 + DOUT_N = DUTN * 8 -verilog.top_harness(DIN_N, DOUT_N) + verilog.top_harness(DIN_N, DOUT_N) -f = open('params.jl', 'w') -f.write('module,loc,params\n') -print( - 'module roi(input clk, input [%d:0] din, output [%d:0] dout);' % - (DIN_N - 1, DOUT_N - 1)) + f = open('params.jl', 'w') + f.write('module,loc,params\n') + print( + 'module roi(input clk, input [%d:0] din, output [%d:0] dout);' % + (DIN_N - 1, DOUT_N - 1)) -for loci, (site_type, site) in enumerate(brams): + for loci, (site_type, site) in enumerate(brams): - def place_bram18(): - ports = { - 'clk': 'clk', - 'din': 'din[ %d +: 8]' % (8 * loci, ), - 'dout': 'dout[ %d +: 8]' % (8 * loci, ), - } + def place_bram18(): + ports = { + 'clk': 'clk', + 'din': 'din[ %d +: 8]' % (8 * loci, ), + 'dout': 'dout[ %d +: 8]' % (8 * loci, ), + } - write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"] + write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"] + collisions = ["DELAYED_WRITE", "PERFORMANCE"] + priorities = ["RSTREG", "REGCE"] - # Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36 - # also 0 and 36 aren't real sizes - # Bias choice to 18 as its needed to solve certain bits quickly - widths = [1, 2, 4, 9, 18, 18, 18, 18] - params = { - 'LOC': verilog.quote(site), - 'IS_CLKARDCLK_INVERTED': vrandbit(), - 'IS_CLKBWRCLK_INVERTED': vrandbit(), - 'IS_ENARDEN_INVERTED': vrandbit(), - 'IS_ENBWREN_INVERTED': vrandbit(), - 'IS_RSTRAMARSTRAM_INVERTED': vrandbit(), - 'IS_RSTRAMB_INVERTED': vrandbit(), - 'IS_RSTREGARSTREG_INVERTED': vrandbit(), - 'IS_RSTREGB_INVERTED': vrandbit(), - 'RAM_MODE': '"TDP"', - 'WRITE_MODE_A': verilog.quote(random.choice(write_modes)), - 'WRITE_MODE_B': verilog.quote(random.choice(write_modes)), - "DOA_REG": vrandbit(), - "DOB_REG": vrandbit(), - "SRVAL_A": vrandbits(18), - "SRVAL_B": vrandbits(18), - "INIT_A": vrandbits(18), - "INIT_B": vrandbits(18), - "READ_WIDTH_A": random.choice(widths), - "READ_WIDTH_B": random.choice(widths), - "WRITE_WIDTH_A": random.choice(widths), - "WRITE_WIDTH_B": random.choice(widths), - } + # Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36 + # also 0 and 36 aren't real sizes + # Bias choice to 18 as its needed to solve certain bits quickly + widths = [1, 2, 4, 9, 18, 18, 18, 18] + params = { + 'LOC': verilog.quote(site), + 'IS_CLKARDCLK_INVERTED': vrandbit(), + 'IS_CLKBWRCLK_INVERTED': vrandbit(), + 'IS_ENARDEN_INVERTED': vrandbit(), + 'IS_ENBWREN_INVERTED': vrandbit(), + 'IS_RSTRAMARSTRAM_INVERTED': vrandbit(), + 'IS_RSTRAMB_INVERTED': vrandbit(), + 'IS_RSTREGARSTREG_INVERTED': vrandbit(), + 'IS_RSTREGB_INVERTED': vrandbit(), + 'RAM_MODE': '"TDP"', + 'WRITE_MODE_A': verilog.quote(random.choice(write_modes)), + 'WRITE_MODE_B': verilog.quote(random.choice(write_modes)), + "DOA_REG": vrandbit(), + "DOB_REG": vrandbit(), + "SRVAL_A": vrandbits(18), + "SRVAL_B": vrandbits(18), + "INIT_A": vrandbits(18), + "INIT_B": vrandbits(18), + "READ_WIDTH_A": random.choice(widths), + "READ_WIDTH_B": random.choice(widths), + "WRITE_WIDTH_A": random.choice(widths), + "WRITE_WIDTH_B": random.choice(widths), + "RDADDR_COLLISION_HWCONFIG": verilog.quote(random.choice(collisions)), + "RSTREG_PRIORITY_A": verilog.quote(random.choice(priorities)), + "RSTREG_PRIORITY_B": verilog.quote(random.choice(priorities)), + } - return ('my_RAMB18E1', ports, params) + return ('my_RAMB18E1', ports, params) - ''' - def place_bram36(): - ports = { - 'clk': 'clk', - 'din': 'din[ %d +: 8]' % (8 * loci, ), - 'dout': 'dout[ %d +: 8]' % (8 * loci, ), - } - params = { - 'LOC': verilog.quote(site), - 'IS_CLKARDCLK_INVERTED': vrandbit(), - 'IS_CLKBWRCLK_INVERTED': vrandbit(), - 'IS_ENARDEN_INVERTED': vrandbit(), - 'IS_ENBWREN_INVERTED': vrandbit(), - 'IS_RSTRAMARSTRAM_INVERTED': vrandbit(), - 'IS_RSTRAMB_INVERTED': vrandbit(), - 'IS_RSTREGARSTREG_INVERTED': vrandbit(), - 'IS_RSTREGB_INVERTED': vrandbit(), - 'RAM_MODE': '"TDP"', - 'WRITE_MODE_A': '"WRITE_FIRST"', - 'WRITE_MODE_B': '"WRITE_FIRST"', - } - return ('my_RAMB36E1', ports, params) - ''' + modname, ports, params = { + 'RAMB18E1': place_bram18, + #'RAMBFIFO36E1': place_bram36, + }[site_type]() - modname, ports, params = { - 'RAMB18E1': place_bram18, - #'RAMBFIFO36E1': place_bram36, - }[site_type]() + verilog.instance(modname, 'inst_%u' % loci, ports, params=params) - verilog.instance(modname, 'inst_%u' % loci, ports, params=params) + j = {'module': modname, 'i': loci, 'params': params} + f.write('%s\n' % (json.dumps(j))) + print('') - j = {'module': modname, 'i': loci, 'params': params} - f.write('%s\n' % (json.dumps(j))) + f.close() + print( + '''endmodule + + // --------------------------------------------------------------------- + + ''') + + # RAMB18E1 + print( + ''' + module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + parameter RAM_MODE = "TDP"; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + + parameter DOA_REG = 1'b0; + parameter DOB_REG = 1'b0; + parameter SRVAL_A = 18'b0; + parameter SRVAL_B = 18'b0; + parameter INIT_A = 18'b0; + parameter INIT_B = 18'b0; + + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + ''') + print('''\ + (* LOC=LOC *) + RAMB18E1 #(''') + for i in range(8): + print(" .INITP_%02X(256'b0)," % (i, )) print('') + for i in range(0x40): + print(" .INIT_%02X(256'b0)," % (i, )) + print('') + print( + ''' + .IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED), + .IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED), + .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), + .IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED), + .IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED), + .IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED), + .IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED), + .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), + .RAM_MODE(RAM_MODE), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), -f.close() -print( - '''endmodule + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .INIT_A(INIT_A), + .INIT_B(INIT_B), -// --------------------------------------------------------------------- + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), -''') + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), -# RAMB18E1 -print( - ''' -module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - parameter RAM_MODE = "TDP"; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - parameter DOA_REG = 1'b0; - parameter DOB_REG = 1'b0; - parameter SRVAL_A = 18'b0; - parameter SRVAL_B = 18'b0; - parameter INIT_A = 18'b0; - parameter INIT_B = 18'b0; - - parameter READ_WIDTH_A = 0; - parameter READ_WIDTH_B = 0; - parameter WRITE_WIDTH_A = 0; - parameter WRITE_WIDTH_B = 0; + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B) + ) ram ( + .CLKARDCLK(din[0]), + .CLKBWRCLK(din[1]), + .ENARDEN(din[2]), + .ENBWREN(din[3]), + .REGCEAREGCE(din[4]), + .REGCEB(din[5]), + .RSTRAMARSTRAM(din[6]), + .RSTRAMB(din[7]), + .RSTREGARSTREG(din[0]), + .RSTREGB(din[1]), + .ADDRARDADDR(din[2]), + .ADDRBWRADDR(din[3]), + .DIADI(din[4]), + .DIBDI(din[5]), + .DIPADIP(din[6]), + .DIPBDIP(din[7]), + .WEA(din[0]), + .WEBWE(din[1]), + .DOADO(dout[0]), + .DOBDO(dout[1]), + .DOPADOP(dout[2]), + .DOPBDOP(dout[3])); + endmodule ''') -print('''\ - (* LOC=LOC *) - RAMB18E1 #(''') -for i in range(8): - print(" .INITP_%02X(256'b0)," % (i, )) -print('') -for i in range(0x40): - print(" .INIT_%02X(256'b0)," % (i, )) -print('') -print( - ''' - .IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED), - .IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED), - .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), - .IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED), - .IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED), - .IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED), - .IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED), - .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), - .RAM_MODE(RAM_MODE), - .WRITE_MODE_A(WRITE_MODE_A), - .WRITE_MODE_B(WRITE_MODE_B), - .DOA_REG(DOA_REG), - .DOB_REG(DOB_REG), - .SRVAL_A(SRVAL_A), - .SRVAL_B(SRVAL_B), - .INIT_A(INIT_A), - .INIT_B(INIT_B), - - .READ_WIDTH_A(READ_WIDTH_A), - .READ_WIDTH_B(READ_WIDTH_B), - .WRITE_WIDTH_A(WRITE_WIDTH_A), - .WRITE_WIDTH_B(WRITE_WIDTH_B) - ) ram ( - .CLKARDCLK(din[0]), - .CLKBWRCLK(din[1]), - .ENARDEN(din[2]), - .ENBWREN(din[3]), - .REGCEAREGCE(din[4]), - .REGCEB(din[5]), - .RSTRAMARSTRAM(din[6]), - .RSTRAMB(din[7]), - .RSTREGARSTREG(din[0]), - .RSTREGB(din[1]), - .ADDRARDADDR(din[2]), - .ADDRBWRADDR(din[3]), - .DIADI(din[4]), - .DIBDI(din[5]), - .DIPADIP(din[6]), - .DIPBDIP(din[7]), - .WEA(din[0]), - .WEBWE(din[1]), - .DOADO(dout[0]), - .DOBDO(dout[1]), - .DOPADOP(dout[2]), - .DOPBDOP(dout[3])); -endmodule -''') - -print( - ''' - -module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - parameter RAM_MODE = "TDP"; - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - ''') -print('') -print('''\ - (* LOC=LOC *) - RAMB36E1 #(''') -for i in range(16): - print(" .INITP_%02X(256'b0)," % (i, )) -print('') -for i in range(0x80): - print(" .INIT_%02X(256'b0)," % (i, )) -print('') -print( - ''' - .IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED), - .IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED), - .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), - .IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED), - .IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED), - .IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED), - .IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED), - .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), - .RAM_MODE(RAM_MODE), - .WRITE_MODE_A(WRITE_MODE_A), - .WRITE_MODE_B(WRITE_MODE_B) - ) ram ( - .CLKARDCLK(din[0]), - .CLKBWRCLK(din[1]), - .ENARDEN(din[2]), - .ENBWREN(din[3]), - .REGCEAREGCE(din[4]), - .REGCEB(din[5]), - .RSTRAMARSTRAM(din[6]), - .RSTRAMB(din[7]), - .RSTREGARSTREG(din[0]), - .RSTREGB(din[1]), - .ADDRARDADDR(din[2]), - .ADDRBWRADDR(din[3]), - .DIADI(din[4]), - .DIBDI(din[5]), - .DIPADIP(din[6]), - .DIPBDIP(din[7]), - .WEA(din[0]), - .WEBWE(din[1]), - .DOADO(dout[0]), - .DOBDO(dout[1]), - .DOPADOP(dout[2]), - .DOPBDOP(dout[3])); -endmodule -''') +if __name__ == "__main__": + main()