From a1b5db694ed3c28a6c2225c47ce9b8003b4af188 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Wed, 6 Apr 2022 05:33:08 +0700 Subject: [PATCH] add XC7K420T support Signed-off-by: Hans Baier --- Makefile | 2 +- fuzzers/005-tilegrid/bram_int/top.py | 12 ++++++++ fuzzers/005-tilegrid/dsp_int/top.py | 12 ++++++++ settings/kintex7_420t.sh | 45 ++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 settings/kintex7_420t.sh diff --git a/Makefile b/Makefile index bf62c3c8..29b80c10 100644 --- a/Makefile +++ b/Makefile @@ -189,7 +189,7 @@ $(foreach DB,$(DATABASES),$(eval $(call database,$(DB)))) ARTIX_PARTS=artix7_50t artix7_200t ZYNQ_PARTS=zynq7010 -KINTEX_PARTS=kintex7_160t kintex7_480t +KINTEX_PARTS=kintex7_160t kintex7_420t kintex7_480t SPARTAN_PARTS= XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} diff --git a/fuzzers/005-tilegrid/bram_int/top.py b/fuzzers/005-tilegrid/bram_int/top.py index 151ba0e3..fb662ce3 100644 --- a/fuzzers/005-tilegrid/bram_int/top.py +++ b/fuzzers/005-tilegrid/bram_int/top.py @@ -14,6 +14,7 @@ import itertools random.seed(int(os.getenv("SEED"), 16)) from prjxray import util from prjxray.db import Database +import re def gen_brams(): @@ -73,9 +74,20 @@ module top(); params = {} + is_kintex_420t="xc7k420t" in os.environ["XRAY_PART"] + sites = list(gen_brams()) fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5)) for tile_name, bram_sites, int_tiles in sites: + # this is a workaround for what looks like a bug + # in Vivado 2017: as soon as I try to instantiate + # more than the 140 rows below then Vivado terminates, + # complaining that it is asked to instantiate more block + # RAM than is available. + bram_y = int(re.sub(".*Y", "", bram_sites[0])) + if is_kintex_420t and bram_y > 139: + continue + # Each BRAM tile has 5 INT tiles. # The following feature is used to toggle a one PIP in each INT tile # diff --git a/fuzzers/005-tilegrid/dsp_int/top.py b/fuzzers/005-tilegrid/dsp_int/top.py index 3a1307b6..88ad543a 100644 --- a/fuzzers/005-tilegrid/dsp_int/top.py +++ b/fuzzers/005-tilegrid/dsp_int/top.py @@ -14,6 +14,7 @@ import itertools random.seed(int(os.getenv("SEED"), 16)) from prjxray import util from prjxray.db import Database +import re def gen_dsps(): @@ -73,9 +74,20 @@ module top(); params = {} + is_kintex_420t="xc7k420t" in os.environ["XRAY_PART"] + sites = list(gen_dsps()) fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5)) for tile_name, dsp_sites, int_tiles in sites: + # this is a workaround for what looks like a bug + # in Vivado 2017: as soon as I try to instantiate + # more than the 140 rows below then Vivado terminates, + # complaining that it is asked to instantiate more block + # RAM than is available. + dsp_y = int(re.sub(".*Y", "", dsp_sites[0])) + if is_kintex_420t and dsp_y > 139: + continue + int_tiles.reverse() # Each DSP tile has 5 INT tiles. diff --git a/settings/kintex7_420t.sh b/settings/kintex7_420t.sh new file mode 100644 index 00000000..3638c410 --- /dev/null +++ b/settings/kintex7_420t.sh @@ -0,0 +1,45 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +export XRAY_DATABASE="kintex7" +export XRAY_PART="xc7k420tffg1156-2" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + +export XRAY_PIN_00=AL18 +export XRAY_PIN_01=AL19 +export XRAY_PIN_02=AK18 +export XRAY_PIN_03=AK19 + +# All CLB's in part, all BRAM's in part, all DSP's in part. +# tcl queries IOB => don't bother adding +export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X153Y349 DSP48_X0Y0:DSP48_X5Y139 RAMB18_X0Y0:RAMB18_X5Y139 RAMB36_X0Y0:RAMB36_X4Y69" + +export XRAY_EXCLUDE_ROI_TILEGRID="" + +# This is used by fuzzers/005-tilegrid/generate_full.py +# (special handling for frame addresses of certain IOIs -- see the script for details). +# This needs to be changed for any new device! +# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST. +export XRAY_IOI3_TILES="" + +# These settings must remain in sync +export XRAY_ROI="SLICE_X0Y0:SLICE_X153Y349 DSP48_X0Y0:DSP48_X5Y139 RAMB18_X0Y0:RAMB18_X5Y139 RAMB36_X0Y0:RAMB36_X4Y69" +# Part of CMT X0Y1 +export XRAY_ROI_GRID_X1="-1" +export XRAY_ROI_GRID_X2="-1" +# Include VBRK / VTERM +export XRAY_ROI_GRID_Y1="-1" +export XRAY_ROI_GRID_Y2="-1" + +source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh + +env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py) +ENV_RET=$? +if [[ $ENV_RET != 0 ]] ; then + return $ENV_RET +fi +eval $env