From 9fb26b6915f81621d8d9cb9e2b605c7f464cbc45 Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Tue, 25 Jun 2019 09:17:11 +0200 Subject: [PATCH] 005-tilegrid: calculate IOI base address Signed-off-by: Tomasz Michalak --- fuzzers/005-tilegrid/Makefile | 5 ++ fuzzers/005-tilegrid/add_tdb.py | 1 + fuzzers/005-tilegrid/ioi/Makefile | 3 + fuzzers/005-tilegrid/ioi/generate.tcl | 81 +++++++++++++++++++ fuzzers/005-tilegrid/ioi/top.py | 109 ++++++++++++++++++++++++++ 5 files changed, 199 insertions(+) create mode 100644 fuzzers/005-tilegrid/ioi/Makefile create mode 100644 fuzzers/005-tilegrid/ioi/generate.tcl create mode 100644 fuzzers/005-tilegrid/ioi/top.py diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index c587aa0b..0d0b31ba 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -3,6 +3,7 @@ BUILD_DIR=$(FUZDIR)/build TILEGRID_TDB_DEPENDENCIES= TILEGRID_TDB_DEPENDENCIES += iob/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob_int/build/segbits_tilegrid.tdb +TILEGRID_TDB_DEPENDENCIES += ioi/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += monitor/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram_block/build/segbits_tilegrid.tdb @@ -64,6 +65,9 @@ iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json iob_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json cd iob_int && $(MAKE) +ioi/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json + cd ioi && $(MAKE) + mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json cd mmcm && $(MAKE) @@ -133,6 +137,7 @@ clean: cd cfg && $(MAKE) clean cd iob && $(MAKE) clean cd iob_int && $(MAKE) clean + cd ioi && $(MAKE) clean cd mmcm && $(MAKE) clean cd pll && $(MAKE) clean cd ps7_int && $(MAKE) clean diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py index 316db698..b893bd30 100644 --- a/fuzzers/005-tilegrid/add_tdb.py +++ b/fuzzers/005-tilegrid/add_tdb.py @@ -77,6 +77,7 @@ def run(fn_in, fn_out, verbose=False): int_frames, int_words = localutil.get_int_params() tdb_fns = [ ("iob/build/segbits_tilegrid.tdb", 42, 4), + ("ioi/build/segbits_tilegrid.tdb", 42, 4), ("mmcm/build/segbits_tilegrid.tdb", 30, 101), ("pll/build/segbits_tilegrid.tdb", 30, 101), ("monitor/build/segbits_tilegrid.tdb", 30, 101), diff --git a/fuzzers/005-tilegrid/ioi/Makefile b/fuzzers/005-tilegrid/ioi/Makefile new file mode 100644 index 00000000..63410fbc --- /dev/null +++ b/fuzzers/005-tilegrid/ioi/Makefile @@ -0,0 +1,3 @@ +N ?= 24 +GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 20 --dword 3" +include ../fuzzaddr/common.mk diff --git a/fuzzers/005-tilegrid/ioi/generate.tcl b/fuzzers/005-tilegrid/ioi/generate.tcl new file mode 100644 index 00000000..96cf1c4c --- /dev/null +++ b/fuzzers/005-tilegrid/ioi/generate.tcl @@ -0,0 +1,81 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc make_io_pin_sites {} { + # get all possible IOB pins + foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { + set site [get_sites -of_objects $pad] + if {[llength $site] == 0} { + continue + } + if [string match IOB33* [get_property SITE_TYPE $site]] { + dict append io_pin_sites $site $pad + } + } + return $io_pin_sites +} + +proc load_pin_lines {} { + # IOB_X0Y103 clk input + # IOB_X0Y129 do[0] output + + set fp [open "params.csv" r] + gets $fp line + + set pin_lines {} + for {gets $fp line} {$line != ""} {gets $fp line} { + lappend pin_lines [split $line ","] + } + close $fp + return $pin_lines +} + +proc loc_pins {} { + set pin_lines [load_pin_lines] + set io_pin_sites [make_io_pin_sites] + set package_pin_keys [dict keys $io_pin_sites] + + puts "Looping" + for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { + set line [lindex $pin_lines $idx] + puts "$line" + + set site_str [lindex $line 2] + set pin_str [lindex $line 3] + set pad_str [lindex $line 4] + + # Have: site + # Want: pin for site + + set site [get_sites $site_str] + set port [get_ports $pin_str] + set tile [get_tiles -of_objects $site] + + + set pin [dict get $io_pin_sites $pad_str] + set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port + } +} + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + #loc_pins + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] + set_property SEVERITY {Warning} [get_drc_checks NSTD-1] + set_property SEVERITY {Warning} [get_drc_checks UCIO-1] + #set_property IS_ENABLED 0 [get_drc_checks {REQP-83}] + + place_design + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit +} + +run diff --git a/fuzzers/005-tilegrid/ioi/top.py b/fuzzers/005-tilegrid/ioi/top.py new file mode 100644 index 00000000..cfd9536e --- /dev/null +++ b/fuzzers/005-tilegrid/ioi/top.py @@ -0,0 +1,109 @@ +import json +import io +import os +import random +import re +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray import lut_maker +from prjxray import verilog +from prjxray.db import Database + + +def gen_sites(): + db = Database(util.get_db_root()) + grid = db.grid() + for tile_name in sorted(grid.tiles()): + loc = grid.loc_of_tilename(tile_name) + gridinfo = grid.gridinfo_at_loc(loc) + if gridinfo.tile_type.endswith("_SING"): + continue + # Y9 tiles have frame address 1 frame higher than the rest + # Need to investigate what is so special about them + if tile_name.endswith("Y9"): + continue + + sites = [] + for site_name, site_type in gridinfo.sites.items(): + if site_type == 'IDELAYE2': + yield tile_name, site_name + + +def write_params(params): + pinstr = 'tile,isone,site\n' + for vals in params: + pinstr += ','.join(map(str, vals)) + '\n' + + open('params.csv', 'w').write(pinstr) + + +def use_idelay(p, luts, connects): + print( + ''' + wire idelay_{site}; + + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + IDELAYE2 #( + .HIGH_PERFORMANCE_MODE("{param}"), + .DELAY_SRC("DATAIN") + ) idelay_site_{site} ( + .DATAIN({onet}), + .DATAOUT(idelay_{site}) + ); + assign {net} = idelay_{site}; + '''.format( + onet=luts.get_next_output_net(), + net=luts.get_next_input_net(), + param="TRUE" if p['isone'] else "FALSE", + **p), + file=connects) + + +def run(): + luts = lut_maker.LutMaker() + connects = io.StringIO() + + tile_params = [] + params = [] + sites = sorted(list(gen_sites())) + for idx, ((tile, site), isone) in enumerate(zip( + sites, util.gen_fuzz_states(len(sites)))): + + p = {} + p['tile'] = tile + p['site'] = site + p['isone'] = isone + params.append(p) + tile_params.append((tile, p['isone'], site)) + + write_params(tile_params) + + print(''' +module top(); + ''') + + # Always output a LUT6 to make placer happy. + print(''' + (* KEEP, DONT_TOUCH *) + LUT6 dummy_lut(); + ''') + + # Need IDELAYCTRL for IDEALAYs + print(''' + (* KEEP, DONT_TOUCH *) + IDELAYCTRL(); + ''') + + for p in params: + use_idelay(p, luts, connects) + + for l in luts.create_wires_and_luts(): + print(l) + + print(connects.getvalue()) + + print("endmodule") + + +if __name__ == '__main__': + run()