From 99d31d2e673b6a7f50f03bbb4d22cb5eadc54f33 Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Thu, 7 Nov 2019 15:02:30 +0100
Subject: [PATCH] 071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 fuzzers/071-ppips/generate.tcl | 30 ++++++++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl
index 16b66ada..1ed6b36a 100644
--- a/fuzzers/071-ppips/generate.tcl
+++ b/fuzzers/071-ppips/generate.tcl
@@ -83,6 +83,24 @@ proc write_bram_ppips_db {filename tile} {
     close $fp
 }
 
+proc write_hclk_ppips_db {filename tile} {
+    set fp [open $filename "w"]
+    set tile [get_tiles $tile]
+    set tile_type [get_property TILE_TYPE $tile]
+
+    foreach pip [get_pips -of_objects $tile] {
+        set dst_wire [get_wires -downhill -of_objects $pip]
+        if [string match "*HCLK_IOI_CK_IGCLK*" $dst_wire] {
+            continue
+        } elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
+            set src_wire [get_wires -uphill -of_objects $pip]
+            puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
+        }
+    }
+
+    close $fp
+}
+
 foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
     set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
     if {[llength $tiles] != 0} {
@@ -100,14 +118,22 @@ foreach tile_type {INT_L INT_R  BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \
             CMT_TOP_L_LOWER_T CMT_TOP_L_LOWER_B \
             CMT_TOP_R_UPPER_T CMT_TOP_R_UPPER_B \
             CMT_TOP_R_LOWER_T CMT_TOP_R_LOWER_B \
-            INT_INTERFACE_L INT_INTERFACE_R \
-            HCLK_IOI3} {
+            INT_INTERFACE_L INT_INTERFACE_R} {
     set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
     if {[llength $tiles] != 0} {
         set tile [lindex $tiles 0]
         write_int_ppips_db "ppips_[string tolower $tile_type].db" $tile
     }
 }
+
+foreach tile_type {HCLK_IOI3} {
+    set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
+    if {[llength $tiles] != 0} {
+        set tile [lindex $tiles 0]
+        write_hclk_ppips_db "ppips_[string tolower $tile_type].db" $tile
+    }
+}
+
 foreach tile_type {BRAM_L BRAM_R} {
     set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
     if {[llength $tiles] != 0} {