diff --git a/fuzzers/010-clb-lutinit/README.md b/fuzzers/010-clb-lutinit/README.md
new file mode 100644
index 00000000..5d3e91e5
--- /dev/null
+++ b/fuzzers/010-clb-lutinit/README.md
@@ -0,0 +1,7 @@
+# clb-lutinit Fuzzer
+
+## NLUT.INIT
+
+Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
+
+Sets the LUT6 INIT property
diff --git a/fuzzers/011-clb-ffconfig/README.md b/fuzzers/011-clb-ffconfig/README.md
index 76874055..e58b766e 100644
--- a/fuzzers/011-clb-ffconfig/README.md
+++ b/fuzzers/011-clb-ffconfig/README.md
@@ -1,61 +1,110 @@
-# FFConfig Fuzzer
+# clb-ffconfig Fuzzer
 
-Documents the following:  
-- FF clock inversion  
-- FF primitive mapping  
-- FF initialization value  
+Documents FF configuration.
 
-Clock inversion is per slice (as BEL CLKINV)  
-Vivado GUI is misleading as it often shows it per FF, which is not actually true  
+Note Vivado GUI is misleading in some cases where it shows configuration per FF, but its actually per SLICE
 
-|      |FFSYNC|LATCH|ZRST |
-|------|------|-----|-----|
-|Sample| 00_48|30_32|30_12|
-|FDPE  |      |     |     |
-|FDSE  |   X  |     |     |
-|FDRE  |   X  |     |  X  |
-|FDCE  |      |     |  X  |
-|LDCE  |      |  X  |  X  |
-|LDPE  |      |  X  |     |
+## Primitive pin map
+
+|  Element | CE | CK | D | SR  | Q |
+|----------|----|----|---|-----|---|
+| FDRE     | CE | C  | D | R   | Q |
+| FDPE     | CE | C  | D | PRE | Q |
+| FDSE     | CE | C  | D | S   | Q |
+| FDCE     | CE | C  | D | CLR | Q |
+| LDPE     | GE | G  | D | PRE | Q |
+| LDCE     | GE | G  | D | CLR | Q |
 
 
-```
-CLB.SLICE_X0.A5FF.ZINIT 31_06
-CLB.SLICE_X0.A5FF.ZRESET 01_07
-CLB.SLICE_X0.AFF.ZINIT 31_03
-CLB.SLICE_X0.AFF.ZRESET 30_12
-CLB.SLICE_X0.B5FF.ZINIT 31_22
-CLB.SLICE_X0.B5FF.ZRESET 01_19
-CLB.SLICE_X0.BFF.ZINIT 31_28
-CLB.SLICE_X0.BFF.ZRESET 30_30
-CLB.SLICE_X0.C5FF.ZINIT 31_41
-CLB.SLICE_X0.C5FF.ZRESET 01_47
-CLB.SLICE_X0.CFF.ZINIT 31_33
-CLB.SLICE_X0.CFF.ZRESET 30_33
-CLB.SLICE_X0.CLKINV 01_51
-CLB.SLICE_X0.D5FF.ZINIT 31_51
-CLB.SLICE_X0.D5FF.ZRESET 01_55
-CLB.SLICE_X0.DFF.ZINIT 31_58
-CLB.SLICE_X0.DFF.ZRESET 30_50
-CLB.SLICE_X0.FFSYNC 00_48
-CLB.SLICE_X0.LATCH 30_32
-CLB.SLICE_X1.A5FF.ZINIT 31_05
-CLB.SLICE_X1.A5FF.ZRESET 01_03
-CLB.SLICE_X1.AFF.ZINIT 31_04
-CLB.SLICE_X1.AFF.ZRESET 31_15
-CLB.SLICE_X1.B5FF.ZINIT 31_23
-CLB.SLICE_X1.B5FF.ZRESET 00_16
-CLB.SLICE_X1.BFF.ZINIT 31_29
-CLB.SLICE_X1.BFF.ZRESET 31_30
-CLB.SLICE_X1.C5FF.ZINIT 31_42
-CLB.SLICE_X1.C5FF.ZRESET 00_44
-CLB.SLICE_X1.CFF.ZINIT 31_34
-CLB.SLICE_X1.CFF.ZRESET 30_34
-CLB.SLICE_X1.CLKINV 00_52
-CLB.SLICE_X1.D5FF.ZINIT 31_52
-CLB.SLICE_X1.D5FF.ZRESET 00_56
-CLB.SLICE_X1.DFF.ZINIT 31_59
-CLB.SLICE_X1.DFF.ZRESET 31_50
-CLB.SLICE_X1.FFSYNC 01_31
-CLB.SLICE_X1.LATCH 31_32
-```
+## Primitive bit map
+
+| Prim | FFSYNC | LATCH | ZRST |
+|------|--------|-------|------|
+|FDPE  |        |       |      |
+|FDSE  | X      |       |      |
+|FDRE  | X      |       | X    |
+|FDCE  |        |       | X    |
+|LDCE  |        | X     | X    |
+|LDPE  |        | X     |      |
+
+
+### FFSYNC
+
+Configures whether a storage element is synchronous or asynchronous.
+
+Scope: entire site (not individual FFs)
+
+| FFSYNC | Reset        | Applicable prims          | 
+|--------|--------------|---------------------------|
+|0       | Synchronous  | FDPE, FDCE, LDCE, LDPE    |
+|1       | Asynchronous | FDSE, FDRE                |
+
+
+### LATCH
+
+Configures latch vs FF behavior for the CLB
+
+| LATCH | Description | Primitives |
+|-------|-------------|------------|
+|0      | All storage elements in the CLB are FF's  | FDPE, FDSE, FDRE, FDCE    |
+|1      | LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used  | LDCE, LDPE    |
+
+
+### N*FF.ZRST
+
+Configures stored value when reset is asserted
+
+| Prim                  |ZRST|On reset|
+|-----------------------|----|-----   |
+|FDRE, FDCE, and LDCE   | 0  | 1      |
+|FDRE, FDCE, and LDCE   | 1  | 0      |
+|FDPE, FDSE, and LDPE   | 0  | 0      |
+|FDPE, FDSE, and LDPE   | 1  | 1      |
+
+
+## N*FF.ZINI
+
+Sets GSR FF or latch value
+
+| LATCH | ZINI | Set to |
+|-------|------|--------|
+| FF    | 0    | 1      |
+| FF    | 1    | 0      |
+| LATCH | 0    | 0      |
+| LATCH | 1    | 1      |
+
+
+## CEUSEDMUX
+
+Configures ability to drive clock enable (CE) or always enable clock
+
+| CEUSEDMUX | Description             |
+|-----------|-------------------------|
+| 0         | always on (CE=1)        |
+| 1         | controlled (CE=mywire)  |
+
+
+## SRUSEDMUX
+
+Configures ability to reset FF after GSR
+
+| SRUSEDMUX | Description           |
+|-----------|-----------------------|
+| 0         | never reset (R=0)     |
+| 1         | controlled (R=mywire) |
+
+TODO: how used when SR?
+
+## CLKINV
+
+Configures whether to invert the clock going into a slice.
+
+Scope: entire site (not individual FFs)
+
+| LATCH | CLKINV | Description    |
+|-------|--------|----------------|
+| FF    | 0      | normal clock   |
+| FF    | 1      | invert clock   |
+| LATCH | 0      | invert clock   |
+| LATCH | 1      | normal clock   |
+
diff --git a/fuzzers/012-clb-n5ffmux/README.md b/fuzzers/012-clb-n5ffmux/README.md
index e0a998fd..46cbf25e 100644
--- a/fuzzers/012-clb-n5ffmux/README.md
+++ b/fuzzers/012-clb-n5ffmux/README.md
@@ -1,18 +1,11 @@
-# CLBn5FFMUX Fuzzer
+# clb-n5ffmux Fuzzer
 
-## Purpose
-Document A5FFMUX family of CLB muxes
+## N5FFMUX
 
-## Algorithm
-5FFMUX  
-Inputs can come from either the LUT6_2 NO5 output or the CLB NX input  
-To perturb the CLB the smallest, want LUT6 always instantiated  
-However, some routing congestion that would require putting FFs in bypass  
-(which turns out is actually okay, but didn't realize that at the time)  
-Decided instead ot instantiate LUT8, but not use the output  
-Turns out this is okay and won't optimize things away  
-So then, the 5FF D input is switched between the O5 output and an external CLB input  
+The A5FFMUX family of CLB muxes feed the D input of A5FF family of FFs
 
-## Outcome
-Bits are one hot encoded per mux position
+| N5FFMUX  | N5FFMUX.D       | 
+|--------|-----------------|
+| IN_A   | N5LUT.O5        |
+| IN_B   | NX              |
 
diff --git a/fuzzers/013-clb-ncy0/README.md b/fuzzers/013-clb-ncy0/README.md
index c9154e98..f2efb164 100644
--- a/fuzzers/013-clb-ncy0/README.md
+++ b/fuzzers/013-clb-ncy0/README.md
@@ -1,8 +1,11 @@
-# CLBnCY0 Fuzzer
+# clb-ncy0 Fuzzer
 
-## Purpose
-Document ACY0 family of CLB muxes
+## CARRY4.NCY0
 
-## Algorithm
+The ACY0 family of CLB muxes feeds the CARRY4.DI0 family
+
+| NCY0  | CARRY4.DIN       | 
+|--------|------------------|
+| 0      | NX               |
+| 1      | O5               |
 
-## Outcome
\ No newline at end of file
diff --git a/fuzzers/014-clb-ffsrcemux/README.md b/fuzzers/014-clb-ffsrcemux/README.md
index 97be91bd..bab6736b 100644
--- a/fuzzers/014-clb-ffsrcemux/README.md
+++ b/fuzzers/014-clb-ffsrcemux/README.md
@@ -1,23 +1,23 @@
-# FFSRCEMUX Fuzzer
+# clb-ffsrcemux Fuzzer
 
-## Purpose
-Document CEUSEDMUX, SRUSEDMUX muxes
+## CEUSEDMUX
 
-## Algorithm
+Configures whether clock enable (CE) is used or clock always on
 
-## Results
-
-### CEUSEDMUX: whether clock enable (CE) is used or clock always on
-0: always on  
-1: controlled  
-CLB.SLICE_X0.CEUSEDMUX 00_39  
-CLB.SLICE_X1.CEUSEDMUX <0 candidates>  
+| CEUSEDMUX  | CE               | 
+|------------|------------------|
+| 0          | Always on        |
+| 1          | Controlled       |
 
 
-### SRUSEDMUX: whether FF can be reset or simply uses D value
-(How used when SR?)  
-0: never reset  
-1: controlled  
-CLB.SLICE_X0.SRUSEDMUX 00_35  
-CLB.SLICE_X1.SRUSEDMUX <0 candidates>  
+### SRUSEDMUX
+
+Configures whether FF can be reset or simply uses D value
+
+| SRUSEDMUX  | Resettable?      | 
+|------------|------------------|
+| 0          | No               |
+| 1          | Controlled       |
+
+XXX: How used when SR?
 
diff --git a/fuzzers/015-clb-nffmux/README.md b/fuzzers/015-clb-nffmux/README.md
index 361b35fd..35ec2094 100644
--- a/fuzzers/015-clb-nffmux/README.md
+++ b/fuzzers/015-clb-nffmux/README.md
@@ -1,41 +1,8 @@
-# CLBnFFMUX Fuzzer
+# clb-nffmux Fuzzer
+
+## NFFMUX
+
+Configures the AFFMUX family of CLB muxes which feed the D input of the AFF series of FFs.
+
+Availible selections varies by A/B/C/D, see db for details.
 
-## Purpose  
-Document nFFMUX family of CLB muxes  
-## Algorithm  
-  
-## Outcome
-```
-CLB.SLICE_X0.AFFMUX.B0 30_00  
-CLB.SLICE_X0.AFFMUX.B1 30_01  
-CLB.SLICE_X0.AFFMUX.B2 30_02  
-CLB.SLICE_X0.AFFMUX.B3 30_03  
-CLB.SLICE_X0.BFFMUX.B0 30_27  
-CLB.SLICE_X0.BFFMUX.B1 30_26  
-CLB.SLICE_X0.BFFMUX.B2 30_25  
-CLB.SLICE_X0.BFFMUX.B3 30_24  
-CLB.SLICE_X0.CFFMUX.B0 30_35  
-CLB.SLICE_X0.CFFMUX.B1 30_36  
-CLB.SLICE_X0.CFFMUX.B2 30_37  
-CLB.SLICE_X0.CFFMUX.B3 30_38  
-CLB.SLICE_X0.DFFMUX.B0 30_62  
-CLB.SLICE_X0.DFFMUX.B1 30_61  
-CLB.SLICE_X0.DFFMUX.B2 30_60  
-CLB.SLICE_X0.DFFMUX.B3 30_59  
-CLB.SLICE_X1.AFFMUX.B0 31_00  
-CLB.SLICE_X1.AFFMUX.B1 31_01  
-CLB.SLICE_X1.AFFMUX.B2 31_02  
-CLB.SLICE_X1.AFFMUX.B3 30_04  
-CLB.SLICE_X1.BFFMUX.B0 31_25  
-CLB.SLICE_X1.BFFMUX.B1 31_27  
-CLB.SLICE_X1.BFFMUX.B2 31_26  
-CLB.SLICE_X1.BFFMUX.B3 31_24  
-CLB.SLICE_X1.CFFMUX.B0 31_35  
-CLB.SLICE_X1.CFFMUX.B1 31_38  
-CLB.SLICE_X1.CFFMUX.B2 31_37  
-CLB.SLICE_X1.CFFMUX.B3 31_36  
-CLB.SLICE_X1.DFFMUX.B0 30_58  
-CLB.SLICE_X1.DFFMUX.B1 31_61  
-CLB.SLICE_X1.DFFMUX.B2 31_62  
-CLB.SLICE_X1.DFFMUX.B3 31_60  
-```
\ No newline at end of file
diff --git a/fuzzers/016-clb-noutmux/README.md b/fuzzers/016-clb-noutmux/README.md
index f330c9a8..287a86f9 100644
--- a/fuzzers/016-clb-noutmux/README.md
+++ b/fuzzers/016-clb-noutmux/README.md
@@ -1,52 +1,8 @@
-# CLBnOUTMUX Fuzzer
+# clb-noutmux Fuzzer
+
+## [A-D]FFMUX
+
+Configures the AOUTMUX family of CLB muxes which feed the AMUX family of CLB outputs
+
+Availible selections varies by A/B/C/D, see db for details.
 
-## Purpose  
-Document nOUTMUX family of CLB muxes  
-## Algorithm  
-  
-## Outcome  
-```
-CLB.SLICE_X0.AOUTMUX.B0 30_11  
-CLB.SLICE_X0.AOUTMUX.B1 30_08  
-CLB.SLICE_X0.AOUTMUX.B2 30_06  
-CLB.SLICE_X0.AOUTMUX.B3 30_07  
-CLB.SLICE_X0.BOUTMUX.B0 30_20  
-CLB.SLICE_X0.BOUTMUX.B1 30_21  
-CLB.SLICE_X0.BOUTMUX.B2 30_22  
-CLB.SLICE_X0.BOUTMUX.B3 30_23  
-CLB.SLICE_X0.COUTMUX.B0 30_45  
-CLB.SLICE_X0.COUTMUX.B1 30_44  
-CLB.SLICE_X0.COUTMUX.B2 30_40  
-CLB.SLICE_X0.COUTMUX.B3 30_43  
-CLB.SLICE_X0.DOUTMUX.B0 30_56  
-CLB.SLICE_X0.DOUTMUX.B1 30_51  
-CLB.SLICE_X0.DOUTMUX.B2 30_52  
-CLB.SLICE_X0.DOUTMUX.B3 30_57  
-CLB.SLICE_X1.AOUTMUX.B0 31_09  
-CLB.SLICE_X1.AOUTMUX.B1 31_07  
-CLB.SLICE_X1.AOUTMUX.B2 31_10  
-CLB.SLICE_X1.AOUTMUX.B3 30_05  
-CLB.SLICE_X1.BOUTMUX.B0 31_20  
-CLB.SLICE_X1.BOUTMUX.B1 30_28  
-CLB.SLICE_X1.BOUTMUX.B2 31_21  
-CLB.SLICE_X1.BOUTMUX.B3 30_29  
-CLB.SLICE_X1.COUTMUX.B0 31_43  
-CLB.SLICE_X1.COUTMUX.B1 30_42  
-CLB.SLICE_X1.COUTMUX.B2 31_40  
-CLB.SLICE_X1.COUTMUX.B3 30_41  
-CLB.SLICE_X1.DOUTMUX.B0 31_56  
-CLB.SLICE_X1.DOUTMUX.B1 30_53  
-CLB.SLICE_X1.DOUTMUX.B2 31_57  
-CLB.SLICE_X1.DOUTMUX.B3 31_53  
-```
-From manual O6 testing
-```
-30_11   X0 AOUTMUX O6  
-30_20   X0 BOUTMUX O6  
-30_45   X0 COUTMUX O6  
-30_56   X0 DOUTMUX O6  
-31_09   X1 AOUTMUX O6  
-31_20   X1 BOUTMUX O6  
-31_43   X1 COUTMUX O6  
-31_56   X1 DOUTMUX O6  
-```
\ No newline at end of file
diff --git a/fuzzers/017-clb-precyinit/README.md b/fuzzers/017-clb-precyinit/README.md
index 886db81d..96cf7373 100644
--- a/fuzzers/017-clb-precyinit/README.md
+++ b/fuzzers/017-clb-precyinit/README.md
@@ -1,19 +1,13 @@
-# CLBPRECYINIT Fuzzer
+# clb-precyinit Fuzzer
 
-## Purpose
-Document PRECYINIT mux
+## PRECYINIT
 
-## Algorithm
+Configures the PRECYINIT mux which provides CARRY4's first carry chain input
 
-## Outcome
+| PRECYINIT  | Value                           | 
+|------------|---------------------------------|
+| C0         | Logic 0                         |
+| C1         | Logic 1                         |
+| AX         | AX CLB input                    |
+| CIN        | Carry in from adjacent CLB COUT |
 
-```
-CLB.SLICE_X0.PRECYINIT.0 <0 candidates>
-CLB.SLICE_X0.PRECYINIT.1 00_12
-CLB.SLICE_X0.PRECYINIT.AX 30_14
-CLB.SLICE_X0.PRECYINIT.CIN 30_13
-CLB.SLICE_X1.PRECYINIT.0 <0 candidates>
-CLB.SLICE_X1.PRECYINIT.1 01_11
-CLB.SLICE_X1.PRECYINIT.AX 31_13
-CLB.SLICE_X1.PRECYINIT.CIN 31_12
-```
\ No newline at end of file
diff --git a/fuzzers/018-clb-ram/README.md b/fuzzers/018-clb-ram/README.md
index 5bfd8e73..5c455165 100644
--- a/fuzzers/018-clb-ram/README.md
+++ b/fuzzers/018-clb-ram/README.md
@@ -1,29 +1,50 @@
-# CLBRAM Fuzzer
+# clb-ram Fuzzer
 
-## Purpose  
-Solves SLICEM specific bits:  
-- Shift register LUT (SRL)  
-- Memory size  
-- RAM vs LUT  
-- Related muxes  
+| Primitive  | RAM | SMALL | SRL |
+|------------|-----|-------|-----|
+| LUT6       |     |       |     |
+| SRL16E     |     | X     | X   |
+| SRLC32E    |     |       | X   |
+| RAM32X1S   | X   | X     |     |
+| RAM64X1S   | X   |       |     |
+| RAM32M     | X   | X     |     |
+| RAM32X1D   | X   | X     |     |
+| RAM64M     | X   |       |     |
+| RAM64X1D   | X   |       |     |
+| RAM128X1D  | X   |       |     |
+| RAM256X1S  | X   |       |     |
+| RAM128X1S  | X   |       |     |
+
+
+## NLUT.RAM
+
+Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.
+
+
+## NLUT.SMALL
+
+Seems to be set on smaller primitives.
+
+
+## NLUT.SRL
+
+Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E
+
+
+## WA7USED
+
+Set to 1 to propagate CLB's CX input to WA7
+
+
+## WA8USED
+
+Set to 1 to propagate CLB's BX input to WA8
+
+
+## WEMUX.CE
+
+| WEMUX.CE  | CLB RAM write enable | 
+|-----------|----------------------|
+| 0         | CLB WE input         |
+| 1         | CLB CE input         |
 
-## Algorithm  
-  
-## Outcome
-```
-CLB.SLICE_X0.ALUT.RAM 31_16
-CLB.SLICE_X0.ALUT.SMALL 00_04
-CLB.SLICE_X0.ALUT.SRL 30_16
-CLB.SLICE_X0.BLUT.RAM 31_17
-CLB.SLICE_X0.BLUT.SMALL 00_24
-CLB.SLICE_X0.BLUT.SRL 30_17
-CLB.SLICE_X0.CLUT.RAM 31_46
-CLB.SLICE_X0.CLUT.SMALL 00_28
-CLB.SLICE_X0.CLUT.SRL 30_46
-CLB.SLICE_X0.DLUT.RAM 31_47
-CLB.SLICE_X0.DLUT.SMALL 01_59
-CLB.SLICE_X0.DLUT.SRL 30_47
-CLB.SLICE_X0.WA7USED 00_40
-CLB.SLICE_X0.WA8USED 01_27
-CLB.SLICE_X0.WEMUX.CE 01_23
-```
\ No newline at end of file
diff --git a/fuzzers/019-clb-ndi1mux/README.md b/fuzzers/019-clb-ndi1mux/README.md
index 4ba6a399..714a2148 100644
--- a/fuzzers/019-clb-ndi1mux/README.md
+++ b/fuzzers/019-clb-ndi1mux/README.md
@@ -1,4 +1,8 @@
-# NDI1MUX Fuzzer
+# clb-ndi1mux Fuzzer
 
-See minitest for DI notes
+## NDI1MUX
+
+Configures the NDI1MUX mux which provides the DI1 input on CLB RAM.
+
+Availible selections varies by A/B/C/D, see db for details.