From 98bcd3f4479bc7fd7ce82db17e4ad70e26ac9197 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 28 Jun 2019 10:52:26 +0200 Subject: [PATCH] Added full vivado flow to the Makefile Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 22 ++++++++++++++++++---- minitests/srl/syn.tcl | 11 +++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) create mode 100644 minitests/srl/syn.tcl diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile index bbccc9e2..c1d730c9 100644 --- a/minitests/srl/Makefile +++ b/minitests/srl/Makefile @@ -1,3 +1,4 @@ +SYNTH ?= vivado YOSYS = $(XRAY_DIR)/third_party/yosys/yosys PART = xc7a35tcsg324-1 BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose @@ -9,7 +10,8 @@ SEGPRINT_TARGETS = $(VERILOG_FILES:.v=.segprint.log) all: $(FASM_TARGETS) $(SEGPRINT_TARGETS) clean: - @find . -name "build.*" | xargs rm -rf + @find . -name "build-par.*" | xargs rm -rf + @find . -name "build-syn.*" | xargs rm -rf @rm -f *.edif @rm -f *.bit @rm -f *.bin @@ -18,17 +20,29 @@ clean: @rm -f *.log @rm -f *.dcp -.PHONY: all clean +help: + @echo "Usage: make all [SYNTH=]" + +.PHONY: all clean help $(YOSYS): cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) +ifeq ($(SYNTH), yosys) %.edif: %.v $(YOSYS) $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log +else ifeq ($(SYNTH), vivado) +%.edif: %.v $(YOSYS) + mkdir -p build-syn.$(basename $@) + cd build-syn.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../syn.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +endif + %.bit: %.edif par.tcl - mkdir -p build.$(basename $@) - cd build.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log + mkdir -p build-par.$(basename $@) + cd build-par.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log rm -rf *.backup.log %.fasm: %.bit diff --git a/minitests/srl/syn.tcl b/minitests/srl/syn.tcl new file mode 100644 index 00000000..2bce1beb --- /dev/null +++ b/minitests/srl/syn.tcl @@ -0,0 +1,11 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L + +read_verilog ../$env(PROJECT_NAME).v + +synth_design -top top + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +write_edif -force ../$env(PROJECT_NAME).edif