From 93914d0e94e8667c1cec191a52b2e3dd14c1e8dd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 18 Oct 2017 20:19:41 +0200 Subject: [PATCH] Updates to 011-ffconfig Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- fuzzers/011-ffconfig/Makefile | 2 +- fuzzers/011-ffconfig/generate.py | 11 ++--- fuzzers/011-ffconfig/generate.sh | 2 + fuzzers/011-ffconfig/generate.tcl | 19 ++++---- fuzzers/011-ffconfig/top.v | 72 +++++++++++++++++++++++++++---- 5 files changed, 79 insertions(+), 27 deletions(-) diff --git a/fuzzers/011-ffconfig/Makefile b/fuzzers/011-ffconfig/Makefile index 7dff61f3..030826df 100644 --- a/fuzzers/011-ffconfig/Makefile +++ b/fuzzers/011-ffconfig/Makefile @@ -1,5 +1,5 @@ -N := 1 +N := 3 SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) diff --git a/fuzzers/011-ffconfig/generate.py b/fuzzers/011-ffconfig/generate.py index 91f0dbc7..7e73a7d0 100644 --- a/fuzzers/011-ffconfig/generate.py +++ b/fuzzers/011-ffconfig/generate.py @@ -37,18 +37,15 @@ with open("design_%s.txt" % sys.argv[1], "r") as f: line = line.split() site = line[0] bel = line[1] - init = int(line[2][3]) - cinv = int(line[3][3]) - dinv = int(line[4][3]) - rinv = int(line[5][3]) + ctype = line[2] + init = int(line[3][3]) + cinv = int(line[4][3]) if site not in data: data[site] = dict() data[site]["%s.ZINI" % bel] = 1-init - # data[site]["%s.CINV" % bel] = cinv - # data[site]["%s.DINV" % bel] = dinv - # data[site]["%s.RINV" % bel] = rinv + # data[site]["CLOCK_INV"] = cinv ################################################# diff --git a/fuzzers/011-ffconfig/generate.sh b/fuzzers/011-ffconfig/generate.sh index ca8b6648..877bd0c4 100644 --- a/fuzzers/011-ffconfig/generate.sh +++ b/fuzzers/011-ffconfig/generate.sh @@ -2,6 +2,8 @@ . ../../utils/genheader.sh +echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh + vivado -mode batch -source ../generate.tcl for i in {0..9}; do diff --git a/fuzzers/011-ffconfig/generate.tcl b/fuzzers/011-ffconfig/generate.tcl index 72f2a821..8d5eff0e 100644 --- a/fuzzers/011-ffconfig/generate.tcl +++ b/fuzzers/011-ffconfig/generate.tcl @@ -4,8 +4,9 @@ read_verilog ../top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports rst] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] create_pblock roi add_cells_to_pblock [get_pblocks roi] [get_cells roi] @@ -29,14 +30,13 @@ write_checkpoint -force design.dcp proc write_txtdata {filename} { puts "Writing $filename." set fp [open $filename w] - foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] { + foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE || REF_NAME == FDSE || REF_NAME == FDCE || REF_NAME == FDPE}] { set loc [get_property LOC $cell] set bel [get_property BEL $cell] + set ctype [get_property REF_NAME $cell] set init [get_property INIT $cell] set cinv [get_property IS_C_INVERTED $cell] - set dinv [get_property IS_D_INVERTED $cell] - set rinv [get_property IS_R_INVERTED $cell] - puts $fp "$loc $bel $init $cinv $dinv $rinv" + puts $fp "$loc $bel $ctype $init $cinv" } close $fp } @@ -46,14 +46,13 @@ write_txtdata design_0.txt ######################################## -# Create versions with random bit changes +# Versions with random config changes proc change_design_randomly {} { foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] { + set site_cells [get_cells -of_objects [get_sites -of_objects $cell] -filter {REF_NAME == FDRE || REF_NAME == FDSE || REF_NAME == FDCE || REF_NAME == FDPE}] set_property INIT 1'b[expr int(rand()*2)] $cell - # set_property IS_C_INVERTED 1'b[expr int(rand()*2)] $cell - # set_property IS_D_INVERTED 1'b[expr int(rand()*2)] $cell - # set_property IS_R_INVERTED 1'b[expr int(rand()*2)] $cell + set_property IS_C_INVERTED 1'b[expr int(rand()*2)] $site_cells } } diff --git a/fuzzers/011-ffconfig/top.v b/fuzzers/011-ffconfig/top.v index 50986a05..ebfc088c 100644 --- a/fuzzers/011-ffconfig/top.v +++ b/fuzzers/011-ffconfig/top.v @@ -1,12 +1,15 @@ -module top(input clk, di, output do); +`include "setseed.vh" + +module top(input clk, rst, di, output do); roi roi ( .clk(clk), + .rst(rst), .din(di), .dout(do) ); endmodule -module roi(input clk, input din, output dout); +module roi(input clk, input rst, input din, output dout); localparam integer N = 500; wire [N:0] nets; @@ -14,16 +17,67 @@ module roi(input clk, input din, output dout); assign nets[0] = din; assign dout = nets[N]; + function [31:0] xorshift32(input [31:0] v); + begin + xorshift32 = v; + xorshift32 = xorshift32 ^ (xorshift32 << 13); + xorshift32 = xorshift32 ^ (xorshift32 >> 17); + xorshift32 = xorshift32 ^ (xorshift32 << 5); + end + endfunction + + function [31:0] hash32(input [31:0] v); + begin + hash32 = v ^ `SEED; + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + end + endfunction + genvar i; generate for (i = 0; i < N; i = i+1) begin:ffs - FDRE ff ( - .C(clk), - .D(nets[i]), - .Q(nets[i+1]), - .R(1'b0), - .CE(1'b1) - ); + localparam integer fftype = hash32(i) % 4; + case (fftype) + 0: begin + FDRE ff ( + .C(clk), + .D(nets[i]), + .Q(nets[i+1]), + .R(rst), + .CE(1'b1) + ); + end + 1: begin + FDSE ff ( + .C(clk), + .D(nets[i]), + .Q(nets[i+1]), + .S(rst), + .CE(1'b1) + ); + end + 2: begin + FDCE ff ( + .C(clk), + .D(nets[i]), + .Q(nets[i+1]), + .CLR(rst), + .CE(1'b1) + ); + end + 3: begin + FDPE ff ( + .C(clk), + .D(nets[i]), + .Q(nets[i+1]), + .PRE(rst), + .CE(1'b1) + ); + end + endcase end endgenerate endmodule