diff --git a/fuzzers/005-tilegrid/pcie/top.py b/fuzzers/005-tilegrid/pcie/top.py
index c9184a98..7afc918d 100644
--- a/fuzzers/005-tilegrid/pcie/top.py
+++ b/fuzzers/005-tilegrid/pcie/top.py
@@ -47,7 +47,8 @@ module top(input wire in, output wire out);
         params[tile_name] = (site_name, isone)
 
         attr = "FALSE" if isone else "TRUE"
-        print('''
+        print(
+            '''
     (* KEEP, DONT_TOUCH*)
     PCIE_2_1 #(
         .AER_CAP_PERMIT_ROOTERR_UPDATE("{}")