From 8f5a69655825ebd5d535a9a9335bbd823762a037 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 30 Nov 2017 19:20:38 +0100 Subject: [PATCH] Add hclkpips fuzzer (wip) Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- fuzzers/058-hclkpips/.gitignore | 1 + fuzzers/058-hclkpips/Makefile | 23 +++++++++++++++++ fuzzers/058-hclkpips/generate.py | 43 +++++++++++++++++++++++++++++++ fuzzers/058-hclkpips/generate.sh | 12 +++++++++ fuzzers/058-hclkpips/generate.tcl | 42 ++++++++++++++++++++++++++++++ fuzzers/058-hclkpips/top.v | 3 +++ 6 files changed, 124 insertions(+) create mode 100644 fuzzers/058-hclkpips/.gitignore create mode 100644 fuzzers/058-hclkpips/Makefile create mode 100644 fuzzers/058-hclkpips/generate.py create mode 100644 fuzzers/058-hclkpips/generate.sh create mode 100644 fuzzers/058-hclkpips/generate.tcl create mode 100644 fuzzers/058-hclkpips/top.v diff --git a/fuzzers/058-hclkpips/.gitignore b/fuzzers/058-hclkpips/.gitignore new file mode 100644 index 00000000..87451d1d --- /dev/null +++ b/fuzzers/058-hclkpips/.gitignore @@ -0,0 +1 @@ +/specimen_*/ diff --git a/fuzzers/058-hclkpips/Makefile b/fuzzers/058-hclkpips/Makefile new file mode 100644 index 00000000..a0bd6f00 --- /dev/null +++ b/fuzzers/058-hclkpips/Makefile @@ -0,0 +1,23 @@ + +N := 2 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: $(SPECIMENS_OK) + # ${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_l.segbits $(addsuffix /segdata_clbl[lm]_l.txt,$(SPECIMENS)) + # ${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_r.segbits $(addsuffix /segdata_clbl[lm]_r.txt,$(SPECIMENS)) + +pushdb: + # ${XRAY_MERGEDB} int_l seg_int_l.segbits + # ${XRAY_MERGEDB} int_r seg_int_r.segbits + # ${XRAY_DBFIXUP} + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ + +.PHONY: database pushdb clean + diff --git a/fuzzers/058-hclkpips/generate.py b/fuzzers/058-hclkpips/generate.py new file mode 100644 index 00000000..9a72f9a1 --- /dev/null +++ b/fuzzers/058-hclkpips/generate.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 + +import sys, os, re + +sys.path.append("../../../utils/") +from segmaker import segmaker + +tags = dict() + +print("Preload all tags.") +for arg in sys.argv[1:]: + with open(arg + ".txt", "r") as f: + for line in f: + tile, pip = line.split() + _, pip = pip.split("/") + tile_type, pip = pip.split(".") + src, dst = pip.split("->>") + tag = "%s.%s.%s" % (tile_type, dst, src) + tags[tag] = dst + +for arg in sys.argv[1:]: + print("Processing %s." % arg) + segmk = segmaker(arg + ".bits") + + tiledata = dict() + pipdata = dict() + ignpip = set() + + with open(arg + ".txt", "r") as f: + for line in f: + tile, pip = line.split() + _, pip = pip.split("/") + tile_type, pip = pip.split(".") + src, dst = pip.split("->>") + tag = "%s.%s.%s" % (tile_type, dst, src) + segmk.addtag(tile, tag, 1) + for tag, tag_dst in tags.items(): + if tag_dst != dst: + segmk.addtag(tile, tag, 0) + + segmk.compile() + segmk.write(arg) + diff --git a/fuzzers/058-hclkpips/generate.sh b/fuzzers/058-hclkpips/generate.sh new file mode 100644 index 00000000..9088b14a --- /dev/null +++ b/fuzzers/058-hclkpips/generate.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +source ${XRAY_GENHEADER} + +vivado -mode batch -source ../generate.tcl + +for x in design_*.bit; do + ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y ${x} +done + +python3 ../generate.py $(ls design_*.bit | cut -f1 -d.) + diff --git a/fuzzers/058-hclkpips/generate.tcl b/fuzzers/058-hclkpips/generate.tcl new file mode 100644 index 00000000..337c5f1e --- /dev/null +++ b/fuzzers/058-hclkpips/generate.tcl @@ -0,0 +1,42 @@ +create_project -force -part $::env(XRAY_PART) design design + +read_verilog ../top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] + +create_pblock roi +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +place_design +route_design + +write_checkpoint -force design.dcp + +source ../../../utils/utils.tcl + +if [regexp "_001$" [pwd]] {set tile [get_tiles HCLK_L_X36Y130]} +if [regexp "_002$" [pwd]] {set tile [get_tiles HCLK_R_X37Y130]} + +set net [get_nets o_OBUF] +set pips [get_pips -of_objects $tile] + +for {set i 0} {$i < [llength $pips]} {incr i} { + set pip [lindex $pips $i] + set_property IS_ROUTE_FIXED 0 $net + route_design -unroute -net $net + set n1 [get_nodes -uphill -of_objects $pip] + set n2 [get_nodes -downhill -of_objects $pip] + route_via $net "$n1 $n2" + write_checkpoint -force design_$i.dcp + write_bitstream -force design_$i.bit + set fp [open "design_$i.txt" w] + puts $fp "$tile $pip" + close $fp +} + diff --git a/fuzzers/058-hclkpips/top.v b/fuzzers/058-hclkpips/top.v new file mode 100644 index 00000000..c0e91c58 --- /dev/null +++ b/fuzzers/058-hclkpips/top.v @@ -0,0 +1,3 @@ +module top (input i, output o); + assign o = i; +endmodule