diff --git a/experiments/lutbuf/.gitignore b/experiments/lutbuf/.gitignore
new file mode 100644
index 00000000..932efba0
--- /dev/null
+++ b/experiments/lutbuf/.gitignore
@@ -0,0 +1,2 @@
+/specimen_[0-9][0-9][0-9]/
+/seg_clbl[lm].segbits
diff --git a/experiments/lutbuf/Makefile b/experiments/lutbuf/Makefile
new file mode 100644
index 00000000..81c30c74
--- /dev/null
+++ b/experiments/lutbuf/Makefile
@@ -0,0 +1,22 @@
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: $(SPECIMENS_OK)
+	../../tools/segmatch -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
+
+pushdb:
+	bash ../../utils/mergedb.sh clbll_l seg_clblx.segbits
+	bash ../../utils/mergedb.sh clbll_r seg_clblx.segbits
+	bash ../../utils/mergedb.sh clblm_l seg_clblx.segbits
+	bash ../../utils/mergedb.sh clblm_r seg_clblx.segbits
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits
+
+.PHONY: database pushdb clean
+
diff --git a/experiments/lutbuf/README.txt b/experiments/lutbuf/README.txt
new file mode 100644
index 00000000..29f26c4f
--- /dev/null
+++ b/experiments/lutbuf/README.txt
@@ -0,0 +1,11 @@
+Purpose:
+Try to show there are LUT enable bits ("buffer enable")
+
+Algorithm:
+Generate a design with a bunch of randomly initialized LUT6s
+Generate a list of fully used LUT6s and fully unused LUT6s
+Compare the lists to look for enable bits
+
+Outcome:
+Did not see existance of such bits
+
diff --git a/experiments/lutbuf/generate.py b/experiments/lutbuf/generate.py
new file mode 100644
index 00000000..c7a7adb4
--- /dev/null
+++ b/experiments/lutbuf/generate.py
@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+
+import sys, re
+
+sys.path.append("../../../utils/")
+from segmaker import segmaker
+
+segmk = segmaker("design.bits")
+
+print("Loading tags from design.txt")
+with open("design.txt", "r") as f:
+    for line in f:
+        '''
+		puts $fp "$type $tile $grid_x $grid_y $lut $lut_type $used"
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X14Y100/B5LUT LUT_OR_MEM5 0
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X14Y100/A6LUT LUT_OR_MEM6 1
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X14Y100/A5LUT LUT_OR_MEM5 1
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X15Y100/D6LUT LUT6 0
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X15Y100/D5LUT LUT5 0
+        CLBLM_R CLBLM_R_X11Y100 33 51 SLICE_X15Y100/C6LUT LUT6 1
+        
+        Lets just keep LUT6 for now
+        LUT6
+        LUT_OR_MEM6
+        '''
+        line = line.split()
+        tile_type = line[0]
+        tile_name = line[1]
+        grid_x = line[2]
+        grid_y = line[3]
+        # Other code uses BEL name
+        site_lut_name = line[4]
+        site, lut_name = site_lut_name.split('/')
+        lut_type = line[5]
+        used = int(line[6])
+        if lut_type not in ('LUT6', 'LUT_OR_MEM6'):
+            continue
+
+        which = lut_name[0]
+        segmk.addtag(site, lut_type + '.' + "%cANY" % which, used)
+
+segmk.compile()
+segmk.write()
+
diff --git a/experiments/lutbuf/generate.sh b/experiments/lutbuf/generate.sh
new file mode 100644
index 00000000..d40bb231
--- /dev/null
+++ b/experiments/lutbuf/generate.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+. ../../utils/genheader.sh
+
+echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
+
+vivado -mode batch -source ../generate.tcl
+
+for x in design*.bit; do
+	../../../tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -zy $x
+done
+
+python3 ../generate.py
+
diff --git a/experiments/lutbuf/generate.tcl b/experiments/lutbuf/generate.tcl
new file mode 100644
index 00000000..e3036630
--- /dev/null
+++ b/experiments/lutbuf/generate.tcl
@@ -0,0 +1,54 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+
+create_pblock roi
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
+
+# Get all 6LUT and 5LUT in pblock
+# A6LUT, B6LUT, A5LUT, etc
+set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */*LUT]
+
+set fp [open "design.txt" w]
+foreach lut $luts {
+	    set tile [get_tile -of_objects $lut]
+	    set grid_x [get_property GRID_POINT_X $tile]
+	    set grid_y [get_property GRID_POINT_Y $tile]
+	    set type [get_property TYPE $tile]
+	    set lut_type [get_property TYPE $lut]
+	    set used [get_property IS_USED $lut]
+	    if {$used} {
+    	    # Only keep used LUT6 with all inputs used
+    	    # roi/is[173].lut62
+	        set lutc [get_cells -of_objects $lut]
+	        set ref [get_property REF_NAME $lutc]
+	        # alternative such as LUT3
+	        if {$ref != "LUT6"} {
+	            continue
+            }
+	    }
+
+		puts $fp "$type $tile $grid_x $grid_y $lut $lut_type $used"
+}
+close $fp
+
diff --git a/experiments/lutbuf/top.v b/experiments/lutbuf/top.v
new file mode 100644
index 00000000..a7151577
--- /dev/null
+++ b/experiments/lutbuf/top.v
@@ -0,0 +1,82 @@
+`include "setseed.vh"
+
+`define N 500
+
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 6;
+	localparam integer DOUT_N = `N;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+	roi roi (
+		.clk(clk),
+		.din(din),
+		.dout(dout)
+	);
+endmodule
+
+module roi(input clk, input [5:0] din, output [`N-1:0] dout);
+	function [31:0] xorshift32(input [31:0] v);
+		begin
+			xorshift32 = v;
+			xorshift32 = xorshift32 ^ (xorshift32 << 13);
+			xorshift32 = xorshift32 ^ (xorshift32 >> 17);
+			xorshift32 = xorshift32 ^ (xorshift32 <<  5);
+		end
+	endfunction
+
+	function [31:0] hash32(input [31:0] v);
+		begin
+			hash32 = v ^ `SEED;
+			hash32 = xorshift32(hash32);
+			hash32 = xorshift32(hash32);
+			hash32 = xorshift32(hash32);
+			hash32 = xorshift32(hash32);
+		end
+	endfunction
+
+	function [63:0] hash64(input [31:0] v);
+		begin
+			hash64[63:32] = hash32(v);
+			hash64[31: 0] = hash32(~v);
+		end
+	endfunction
+
+	genvar i;
+	generate
+		for (i = 0; i < `N; i = i+1) begin:is
+			wire o6;
+			//Randomly take out 1/4 iterations
+			wire [3:0] hash = hash32(i);
+			wire opt_out = |hash;
+			assign dout[i] = o6 & opt_out;
+
+			LUT6 #(
+				.INIT(hash64(i))
+			) lut6 (
+				.I0(din[0]),
+				.I1(din[1]),
+				.I2(din[2]),
+				.I3(din[3]),
+				.I4(din[4]),
+				.I5(din[5]),
+				.O(o6)
+			);
+		end
+	endgenerate
+endmodule