From 8cfef55bf422971c81d05b9fc6d49c14073d41fc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Oct 2017 13:06:35 +0200 Subject: [PATCH] Add picorv32 segdata Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- picorv32/.gitignore | 7 ++- picorv32/runme.sh | 26 +++++++---- picorv32/segdata.py | 108 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+), 10 deletions(-) create mode 100644 picorv32/segdata.py diff --git a/picorv32/.gitignore b/picorv32/.gitignore index 43fed1d4..4b30a3eb 100644 --- a/picorv32/.gitignore +++ b/picorv32/.gitignore @@ -4,8 +4,11 @@ /design.tcl /design.xdc /design.bit +/design_roi_partial.bit /design.bits /design.dcp +/hd_visual/ +/vivado[_.]* +/usage_statistics_webtalk.* /lutlist.txt -/vivado.jou -/vivado.log +/segdata.txt diff --git a/picorv32/runme.sh b/picorv32/runme.sh index 712c8124..2610b0ac 100644 --- a/picorv32/runme.sh +++ b/picorv32/runme.sh @@ -14,9 +14,12 @@ set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \ [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical] create_pblock roi -add_cells_to_pblock [get_pblocks roi] [get_cells -quiet [list picorv32]] +add_cells_to_pblock [get_pblocks roi] [get_cells picorv32] resize_pblock [get_pblocks roi] -add {$XRAY_ROI} +# requires partial reconfiguration license +set_property HD.RECONFIGURABLE TRUE [get_cells picorv32] + set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] @@ -42,16 +45,23 @@ puts "Writing lutlist.txt." current_instance picorv32 set fp [open "lutlist.txt" w] set luts [get_cells -filter {REF_NAME == LUT6}] -foreach lut $luts { - set bel [get_property BEL $lut] - set loc [get_property LOC $lut] - set init [get_property INIT $lut] - puts $fp "$loc $bel $init" +foreach lut \$luts { + set bel [get_property BEL \$lut] + set loc [get_property LOC \$lut] + set init [get_property INIT \$lut] + puts \$fp "\$loc \$bel \$init" } -close $fp +close \$fp EOT rm -rf design design.log vivado -nojournal -log design.log -mode batch -source design.tcl -../tools/bitread -o design.bits -zy < design.bit + +if [ -f design_roi_partial.bit ]; then + ../tools/bitread -o design.bits -zy < design_roi_partial.bit +else + ../tools/bitread -o design.bits -zy < design.bit +fi + +python3 segdata.py diff --git a/picorv32/segdata.py b/picorv32/segdata.py new file mode 100644 index 00000000..edccfec5 --- /dev/null +++ b/picorv32/segdata.py @@ -0,0 +1,108 @@ +#!/usr/bin/env python3 + +import os, json, re + +################################################# +# Loading Raw Source Data + +grid = None +bits = dict() +luts = dict() + +print("Loading grid.") +with open("../gridinfo/grid-%s-db.json" % os.getenv("XRAY_PART"), "r") as f: + grid = json.load(f) + +print("Loading bits.") +with open("design.bits", "r") as f: + for line in f: + line = line.split("_") + bit_frame = int(line[1], 16) + bit_wordidx = int(line[2], 16) + bit_bitidx = int(line[3], 16) + base_frame = bit_frame & ~0x7f + + if base_frame not in bits: + bits[base_frame] = dict() + + if bit_wordidx not in bits[base_frame]: + bits[base_frame][bit_wordidx] = set() + + bits[base_frame][bit_wordidx].add((bit_frame, bit_wordidx, bit_bitidx)) + +print("Loading luts.") +with open("lutlist.txt", "r") as f: + for line in f: + line = line.split() + site = line[0] + bel = line[1] + init = int(line[2][4:], 16) + + if site not in luts: + luts[site] = dict() + + for i in range(64): + bitname = "%s.INIT[%02d]" % (bel, i) + luts[site][bitname] = ((init >> i) & 1) != 0 + + +################################################# +# Group per Segment + +print("Pivot segment data.") + +segments = dict() + +for tilename, tiledata in grid["tiles"].items(): + found_data = False + for site in tiledata["sites"]: + if site in luts: + found_data = True + + if not found_data: + continue + + segname = "%s_%02x" % (tiledata["cfgcol"]["BASE_FRAMEID"][2:], min(tiledata["cfgcol"]["WORDS"])) + + if not segname in segments: + segments[segname] = { "bits": list(), "tags": dict() } + + for site in tiledata["sites"]: + if site not in luts: + continue + + if re.match(r"SLICE_X[0-9]*[02468]Y", site): + sitekey = "SLICE_X0" + elif re.match(r"SLICE_X[0-9]*[13579]Y", site): + sitekey = "SLICE_X1" + else: + assert 0 + + for name, value in luts[site].items(): + segments[segname]["tags"]["%s.%s.%s" % (tiledata["props"]["TYPE"], sitekey, name)] = value + + base_frame = int(tiledata["cfgcol"]["BASE_FRAMEID"][2:], 16) + for wordidx in tiledata["cfgcol"]["WORDS"]: + if base_frame not in bits: + continue + if wordidx not in bits[base_frame]: + continue + for bit_frame, bit_wordidx, bit_bitidx in bits[base_frame][wordidx]: + segments[segname]["bits"].append("%02x_%02x_%02x" % (bit_frame - base_frame, bit_wordidx - min(tiledata["cfgcol"]["WORDS"]), bit_bitidx)) + + segments[segname]["bits"].sort() + + +################################################# +# Print + +print("Write segment data.") + +with open("segdata.txt", "w") as f: + for segname, segdata in sorted(segments.items()): + print("seg %s" % segname, file=f) + for bitname in sorted(segdata["bits"]): + print("bit %s" % bitname, file=f) + for tagname, tagval in sorted(segdata["tags"].items()): + print("tag %s %d" % (tagname, tagval), file=f) +