diff --git a/minitests/util/runme.tcl b/minitests/util/runme.tcl
index 86162f92..8f7bd546 100644
--- a/minitests/util/runme.tcl
+++ b/minitests/util/runme.tcl
@@ -1,6 +1,6 @@
 create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
-synth_design -top top
+synth_design -top top -flatten_hierarchy none
 
 set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
 set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]