From 8c90ae2e395cb00bee5855a5f3e9727826a25c9e Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Wed, 3 Apr 2019 19:28:23 -0700
Subject: [PATCH] docs: Adding DRAM info to TOC.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
---
 docs/index.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/index.rst b/docs/index.rst
index cb08fe45..d9b51b79 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -20,6 +20,7 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    architecture/overview
    architecture/configuration
    architecture/bitstream_format
+   architecture/dram_configuration
    architecture/glossary
 
 .. toctree::