diff --git a/fuzzers/005-tilegrid/clb/generate.tcl b/fuzzers/005-tilegrid/clb/generate.tcl index 5e72d333..26a9b409 100644 --- a/fuzzers/005-tilegrid/clb/generate.tcl +++ b/fuzzers/005-tilegrid/clb/generate.tcl @@ -19,6 +19,46 @@ proc run {} { place_design route_design + create_cell -reference VCC vcc_cell + set vcc_pin [get_pins vcc_cell/P] + + create_net vcc_net + set vcc_net [get_nets vcc_net] + connect_net -net $vcc_net -objects $vcc_pin + + create_cell -reference GND gnd_cell + set gnd_pin [get_pins gnd_cell/G] + + create_net gnd_net + set gnd_net [get_nets gnd_net] + connect_net -net $gnd_net -objects $gnd_pin + + set fp [open params.csv r] + + # Skip header line + gets $fp line + + # This is done post-placement to remove PROHIBIT on some sites. + puts "Creating CARRY4's" + while {[gets $fp line] >= 0} { + set parts [split [string trim $line] ","] + set val [lindex $parts 1] + set site [lindex $parts 2] + + set cell [create_cell -reference CARRY4 carry4_$site] + set_property PROHIBIT 0 [get_sites $site] + set_property KEEP true $cell + set_property DONT_TOUCH 1 $cell + set_property LOC $site $cell + + if { $val == 1 } { + connect_net -net $vcc_net -objects [get_pins carry4_$site/CI] + } else { + connect_net -net $gnd_net -objects [get_pins carry4_$site/CI] + } + } + puts "Done creating CARRY4's" + write_checkpoint -force design.dcp write_bitstream -force design.bit } diff --git a/fuzzers/005-tilegrid/clb/top.py b/fuzzers/005-tilegrid/clb/top.py index f8b24892..9b32b4dd 100644 --- a/fuzzers/005-tilegrid/clb/top.py +++ b/fuzzers/005-tilegrid/clb/top.py @@ -55,13 +55,6 @@ module top(input clk, stb, di, output do); util.gen_fuzz_states(len(sites))): params[tile_name] = (site_name, isone) - print( - ''' - (* KEEP, DONT_TOUCH, LOC = "%s" *) - CARRY4 carry4_%s ( - .CYINIT(%u)); -''' % (site_name, site_name, isone)) - print("endmodule") write_params(params) diff --git a/fuzzers/005-tilegrid/clb_int/generate.tcl b/fuzzers/005-tilegrid/clb_int/generate.tcl index 9e8cab8a..7fed629d 100644 --- a/fuzzers/005-tilegrid/clb_int/generate.tcl +++ b/fuzzers/005-tilegrid/clb_int/generate.tcl @@ -5,11 +5,66 @@ proc run {} { read_verilog top.v synth_design -top top + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] place_design + + create_cell -reference VCC vcc_cell + set vcc_pin [get_pins vcc_cell/P] + + create_net vcc_net + set vcc_net [get_nets vcc_net] + connect_net -net $vcc_net -objects $vcc_pin + + create_cell -reference GND gnd_cell + set gnd_pin [get_pins gnd_cell/G] + + create_net gnd_net + set gnd_net [get_nets gnd_net] + connect_net -net $gnd_net -objects $gnd_pin + + set fp [open params.csv r] + + # Skip header line + gets $fp line + + # This is done post-placement to remove PROHIBIT on some sites. + # + # Force HARD0 -> GFAN1 with I2 = 0 + # Toggle 1 pip with I1 = ? + puts "Creating LUT6's" + while {[gets $fp line] >= 0} { + set parts [split [string trim $line] ","] + set val [lindex $parts 1] + set site [lindex $parts 2] + + set cell [create_cell -reference LUT6 lut6_$site] + + set_property PROHIBIT 0 [get_sites $site] + set_property KEEP true $cell + set_property DONT_TOUCH 1 $cell + set_property BEL D6LUT $cell + set_property LOC $site $cell + + connect_net -net $vcc_net -objects [get_pins lut6_$site/I0] + connect_net -net $gnd_net -objects [get_pins lut6_$site/I2] + connect_net -net $vcc_net -objects [get_pins lut6_$site/I3] + connect_net -net $vcc_net -objects [get_pins lut6_$site/I4] + connect_net -net $vcc_net -objects [get_pins lut6_$site/I5] + + if { $val == 1 } { + connect_net -net $vcc_net -objects [get_pins lut6_$site/I1] + } else { + connect_net -net $gnd_net -objects [get_pins lut6_$site/I1] + } + } + puts "Done creating LUT6's" + route_design write_checkpoint -force design.dcp diff --git a/fuzzers/005-tilegrid/clb_int/top.py b/fuzzers/005-tilegrid/clb_int/top.py index 64671b86..87d5ee1e 100644 --- a/fuzzers/005-tilegrid/clb_int/top.py +++ b/fuzzers/005-tilegrid/clb_int/top.py @@ -35,7 +35,8 @@ def write_params(params): def run(): print(''' -module top(); +module top(input di, output do); + assign do = di; ''') params = {} @@ -45,34 +46,6 @@ module top(); util.gen_fuzz_states(len(sites))): params[tile_name] = (site_name, isone) - # Force HARD0 -> GFAN1 with I2 = 0 - # Toggle 1 pip with I1 = ? - print( - ''' - wire lut_to_f7_{0}, f7_to_f8_{0}; - (* KEEP, DONT_TOUCH, LOC = "{0}" *) - LUT6_L #( - .INIT(0) - ) lut_rom_{0} ( - .I0(1), - .I1({1}), - .I2(0), - .I3(1), - .I4(1), - .I5(1), - .LO(lut_to_f7_{0}) - ); - (* KEEP, DONT_TOUCH, LOC = "{0}" *) - MUXF7_L f7_{0} ( - .I0(lut_to_f7_{0}), - .LO(f7_to_f8_{0}) - ); - (* KEEP, DONT_TOUCH, LOC = "{0}" *) - MUXF8 f8_{0} ( - .I0(f7_to_f8_{0}) - ); -'''.format(site_name, isone)) - print("endmodule") write_params(params) diff --git a/settings/artix200t.sh b/settings/artix200t.sh index 392f00c4..1f5bbe23 100644 --- a/settings/artix200t.sh +++ b/settings/artix200t.sh @@ -6,7 +6,7 @@ export XRAY_ROI_FRAMES="0x00000000:0xffffffff" # tcl queries IOB => don't bother adding export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X163Y249 RAMB18_X0Y0:RAMB18_X8Y99 RAMB36_X0Y0:RAMB36_X8Y49 DSP48_X0Y0:DSP48_X8Y99 IOB_X0Y0:IOB_X1Y249" -export XRAY_EXCLUDE_ROI_TILEGRID="SLICE_X82Y200:SLICE_X83Y249 SLICE_X82Y0:SLICE_X83Y49" +export XRAY_EXCLUDE_ROI_TILEGRID="" export XRAY_IOI3_TILES="RIOI3_X105Y9 LIOI3_X0Y9"