From 3d444052162ae1ed796a74165bed68ca04be641f Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 21 Apr 2020 18:44:41 +0200 Subject: [PATCH 1/3] Re-enabled 037 to fuzz IOI_ILOGIC[01]_CLKB\.IOI_IMUX22_[01] pips. Signed-off-by: Maciej Kurc --- fuzzers/037-iob-pips/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fuzzers/037-iob-pips/Makefile b/fuzzers/037-iob-pips/Makefile index 18f94fbb..3c77db57 100644 --- a/fuzzers/037-iob-pips/Makefile +++ b/fuzzers/037-iob-pips/Makefile @@ -3,7 +3,7 @@ PIP_TYPE?=ioi3 PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl TODO_RE=".*" -EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)|(OCLKM.*IMUX31)|(IOI_ILOGIC[01]_CLKB\.IOI_IMUX22_[01])).*" +EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)|(OCLKM.*IMUX31)).*" MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE) N = 40 From 906bae2b3191d178dbe3024b91078cebe69bf984 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 24 Apr 2020 10:12:33 +0200 Subject: [PATCH 2/3] Changed P&R directive to "quick" Signed-off-by: Maciej Kurc --- fuzzers/037-iob-pips/generate.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fuzzers/037-iob-pips/generate.tcl b/fuzzers/037-iob-pips/generate.tcl index 8d47925f..1aab4b0b 100644 --- a/fuzzers/037-iob-pips/generate.tcl +++ b/fuzzers/037-iob-pips/generate.tcl @@ -44,9 +44,9 @@ proc run {} { set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets] - place_design + place_design -directive Quick write_checkpoint -force design_before_route.dcp - route_design + route_design -directive Quick write_checkpoint -force design.dcp write_bitstream -force design.bit From 28ddeb2feb3fe307bf3ee218cc8a482018f69079 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 28 Apr 2020 12:11:20 +0200 Subject: [PATCH 3/3] Added forced routing through IMUX PIPs. Changed some stimulus. Signed-off-by: Maciej Kurc --- fuzzers/037-iob-pips/generate.tcl | 48 +++++++++++++++++++++++++++- fuzzers/037-iob-pips/top.py | 52 +++++++++++++++++++++---------- 2 files changed, 83 insertions(+), 17 deletions(-) diff --git a/fuzzers/037-iob-pips/generate.tcl b/fuzzers/037-iob-pips/generate.tcl index 1aab4b0b..c5f74c59 100644 --- a/fuzzers/037-iob-pips/generate.tcl +++ b/fuzzers/037-iob-pips/generate.tcl @@ -23,6 +23,51 @@ proc write_pip_txtdata {filename} { close $fp } +proc make_manual_routes {filename} { + puts "MANROUTE: Loading routes from $filename" + + set fp [open $filename r] + foreach line [split [read $fp] "\n"] { + if {$line eq ""} { + continue + } + + puts "MANROUTE: Line: $line" + + # Parse the line + set fields [split $line " "] + set net_name [lindex $fields 0] + set wire_name [lindex $fields 1] + + # Check if that net exist + if {[get_nets $net_name] eq ""} { + puts "MANROUTE: net $net_name does not exist" + continue + } + + set net [get_nets $net_name] + + # Rip it up + set_property -quiet FIXED_ROUTE "" $net + set_property IS_ROUTE_FIXED 0 $net + route_design -unroute -nets $net + + # Make the route + set nodes [get_nodes -of_objects [get_wires $wire_name]] + set status [route_via $net_name [list $nodes] 0] + + # Failure, skip manual routing of this net + if { $status != 1 } { + puts "MANROUTE: Manual routing failed!" + set_property -quiet FIXED_ROUTE "" $net + set_property IS_ROUTE_FIXED 0 $net + continue + } + + puts "MANROUTE: Success!" + } +} + proc run {} { create_project -force -part $::env(XRAY_PART) design design read_verilog top.v @@ -46,7 +91,8 @@ proc run {} { place_design -directive Quick write_checkpoint -force design_before_route.dcp - route_design -directive Quick + make_manual_routes routes.txt + route_design -directive Quick -preserve write_checkpoint -force design.dcp write_bitstream -force design.bit diff --git a/fuzzers/037-iob-pips/top.py b/fuzzers/037-iob-pips/top.py index 283c5ba3..ed5017cd 100644 --- a/fuzzers/037-iob-pips/top.py +++ b/fuzzers/037-iob-pips/top.py @@ -186,6 +186,7 @@ def run(): """ output = [] + route_file = open("routes.txt", "w") for tile in gen_sites(): if tile['tile_type'] in NOT_INCLUDED_TILES: @@ -222,29 +223,48 @@ def run(): oclkb = random.randint(0, 1) DATA_RATE = random.choice(['DDR', 'SDR']) - clk, is_lut = clocks.get_clock( + clk, clk_is_lut = clocks.get_clock( ilogic_site, allow_ioclks=True, allow_rclks=True, allow_empty=DATA_RATE == 'SDR') - if False: - clkb = clk - else: - clkb = clk - if random.randint(0, 1): - while clkb == clk: - clkb, _ = clocks.get_clock( - ilogic_site, - allow_ioclks=True, - allow_rclks=True, - allow_empty=False) - else: - # Explicitly provide IMUX stimulus to resolve IMUX pips - clk = random.randint(0, 1) - clkb = random.randint(0, 1) + + clkb = clk + while clkb == clk: + clkb, clkb_is_lut = clocks.get_clock( + ilogic_site, + allow_ioclks=True, + allow_rclks=True, + allow_empty=False) + + imux_available = { + 0: set(("IOI_IMUX20_0", "IOI_IMUX22_0")), + 1: set(("IOI_IMUX20_1", "IOI_IMUX22_1")), + } + + # Force CLK route through IMUX when connected to a LUT + if clk_is_lut: + y = (xy[1] + 1) % 2 + + route = random.choice(list(imux_available[y])) + imux_available[y].remove(route) + + route = "{}/{}".format(tile["tile"], route) + route_file.write("{} {}\n".format(clk, route)) + + # Force CLKB route through IMUX when connected to a LUT + if clkb_is_lut: + y = (xy[1] + 1) % 2 + + route = random.choice(list(imux_available[y])) + imux_available[y].remove(route) + + route = "{}/{}".format(tile["tile"], route) + route_file.write("{} {}\n".format(clkb, route)) if ilogic_site_type is None: pass + elif ilogic_site_type == 'ISERDESE2': INTERFACE_TYPE = random.choice( [