diff --git a/fuzzers/025-bram-config/generate.py b/fuzzers/025-bram-config/generate.py
index a0eb7831..b9a0a127 100644
--- a/fuzzers/025-bram-config/generate.py
+++ b/fuzzers/025-bram-config/generate.py
@@ -1,17 +1,20 @@
 #!/usr/bin/env python3
 
 import json
+import csv
 
 from prjxray.segmaker import Segmaker
 from prjxray import verilog
 from prjxray import segmaker
 
 
-def isinv_tags(segmk, ps, site):
+def isinv_tags(segmk, ps, site, actual_ps):
     # all of these bits are inverted
     ks = [
         ('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
         ('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
+        ('IS_REGCLKARDRCLK_INVERTED', 'ZINV_REGCLKARDRCLK'),
+        ('IS_REGCLKB_INVERTED', 'ZINV_REGCLKB'),
         ('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
         ('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
         ('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
@@ -19,9 +22,33 @@ def isinv_tags(segmk, ps, site):
         ('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
         ('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
     ]
-    for param, tagname in ks:
-        segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
 
+    for param, tagname in ks:
+        # The CLK inverts sometimes are changed during synthesis, resulting
+        # in addition inversions.  Take this into account.
+        if param in actual_ps:
+            tag = 1 ^ verilog.parsei(actual_ps[param])
+        elif param == 'IS_REGCLKARDRCLK_INVERTED':
+            if verilog.parsei(ps['DOA_REG']):
+                # When DOA_REG == 1, REGCLKARDRCLK follows the CLKARDCLK setting.
+                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKARDCLK_INVERTED'])
+            else:
+                # When DOA_REG == 0, REGCLKARDRCLK is always inverted.
+                tag = 0
+
+            segmk.add_site_tag(site, tagname, tag)
+        elif param == 'IS_REGCLKB_INVERTED':
+            if verilog.parsei(ps['DOB_REG']):
+                # When DOB_REG == 1, REGCLKB follows the CLKBWRCLK setting.
+                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKBWRCLK_INVERTED'])
+            else:
+                # When DOB_REG == 0, REGCLKB is always inverted.
+                tag = 0
+
+        else:
+            tag = 1 ^ verilog.parsei(ps[param])
+
+        segmk.add_site_tag(site, tagname, tag)
 
 def bus_tags(segmk, ps, site):
     for param in ("DOA_REG", "DOB_REG"):
@@ -75,7 +102,11 @@ def write_mode_tags(segmk, ps, site):
 def run():
 
     segmk = Segmaker("design.bits")
-    #segmk.set_def_bt('BLOCK_RAM')
+
+    clk_inverts = {}
+    with open('design.csv', 'r') as f:
+        for params in csv.DictReader(f):
+            clk_inverts[params['site']] = params
 
     print("Loading tags")
     f = open('params.jl', 'r')
@@ -86,7 +117,7 @@ def run():
         assert j['module'] == 'my_RAMB18E1'
         site = verilog.unquote(ps['LOC'])
 
-        isinv_tags(segmk, ps, site)
+        isinv_tags(segmk, ps, site, clk_inverts[site])
         bus_tags(segmk, ps, site)
         rw_width_tags(segmk, ps, site)
         write_mode_tags(segmk, ps, site)
diff --git a/fuzzers/025-bram-config/generate.tcl b/fuzzers/025-bram-config/generate.tcl
index 1a647bb1..ddc0fba2 100644
--- a/fuzzers/025-bram-config/generate.tcl
+++ b/fuzzers/025-bram-config/generate.tcl
@@ -23,3 +23,13 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
+
+set fp [open "design.csv" "w"]
+puts $fp "site,IS_CLKARDCLK_INVERTED,IS_CLKBWRCLK_INVERTED"
+foreach ram [get_cells "roi/inst_*/ram"] {
+    set site [get_sites -of_objects [get_bels -of_objects $ram]]
+    set IS_CLKARDCLK_INVERTED [get_property IS_CLKARDCLK_INVERTED $ram]
+    set IS_CLKBWRCLK_INVERTED [get_property IS_CLKBWRCLK_INVERTED $ram]
+    puts $fp "$site,$IS_CLKARDCLK_INVERTED,$IS_CLKBWRCLK_INVERTED"
+}
+close $fp
diff --git a/fuzzers/025-bram-config/top.py b/fuzzers/025-bram-config/top.py
index 7f34a661..2f0babbb 100644
--- a/fuzzers/025-bram-config/top.py
+++ b/fuzzers/025-bram-config/top.py
@@ -4,7 +4,6 @@ random.seed(int(os.getenv("SEED"), 16))
 from prjxray import util
 from prjxray import verilog
 from prjxray.verilog import vrandbit, vrandbits
-import sys
 import json