diff --git a/minitests/litex/uart_ddr/arty/scripts/arty.py b/minitests/litex/uart_ddr/arty/scripts/arty.py index a6203518..287a4917 100755 --- a/minitests/litex/uart_ddr/arty/scripts/arty.py +++ b/minitests/litex/uart_ddr/arty/scripts/arty.py @@ -21,76 +21,89 @@ from litedram.phy import s7ddrphy # CRG ---------------------------------------------------------------------------------------------- + class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() # # # self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) # BaseSoC ------------------------------------------------------------------------------------------ + class BaseSoC(SoCSDRAM): def __init__(self): - platform = arty.Platform() + platform = arty.Platform() sys_clk_freq = int(50e6) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - ident = "Minimal Arty DDR3 Design for tests with Project X-Ray", ident_version=True, - cpu_type = None, - l2_size = 16, - uart_name = "bridge") + SoCSDRAM.__init__( + self, + platform, + clk_freq=sys_clk_freq, + ident="Minimal Arty DDR3 Design for tests with Project X-Ray", + ident_version=True, + cpu_type=None, + l2_size=16, + uart_name="bridge") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), - memtype = "DDR3", - nphases = 4, - sys_clk_freq = sys_clk_freq) + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + platform.request("ddram"), + memtype="DDR3", + nphases=4, + sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41K128M16(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + self.register_sdram( + self.ddrphy, + geom_settings=sdram_module.geom_settings, + timing_settings=sdram_module.timing_settings) def generate_sdram_phy_py_header(self): f = open("sdram_init.py", "w") - f.write(get_sdram_phy_py_header( - self.sdram.controller.settings.phy, - self.sdram.controller.settings.timing)) + f.write( + get_sdram_phy_py_header( + self.sdram.controller.settings.phy, + self.sdram.controller.settings.timing)) f.close() + # Load --------------------------------------------------------------------------------------------- + def load(): prog = VivadoProgrammer() prog.load_bitstream("build/gateware/top.bit") + # Build -------------------------------------------------------------------------------------------- -def main(): - parser = argparse.ArgumentParser(description="Minimal Arty DDR3 Design for tests with Project X-Ray") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - args = parser.parse_args() +def main(): + parser = argparse.ArgumentParser( + description="Minimal Arty DDR3 Design for tests with Project X-Ray") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + args = parser.parse_args() if args.load: load() @@ -99,5 +112,6 @@ def main(): builder.build(run=args.build) soc.generate_sdram_phy_py_header() + if __name__ == "__main__": main() diff --git a/minitests/litex/uart_ddr/arty/scripts/sdram_init.py b/minitests/litex/uart_ddr/arty/scripts/sdram_init.py index 56103855..80fb3832 100644 --- a/minitests/litex/uart_ddr/arty/scripts/sdram_init.py +++ b/minitests/litex/uart_ddr/arty/scripts/sdram_init.py @@ -1,23 +1,33 @@ -dfii_control_sel = 0x01 -dfii_control_cke = 0x02 -dfii_control_odt = 0x04 +dfii_control_sel = 0x01 +dfii_control_cke = 0x02 +dfii_control_odt = 0x04 dfii_control_reset_n = 0x08 -dfii_command_cs = 0x01 -dfii_command_we = 0x02 -dfii_command_cas = 0x04 -dfii_command_ras = 0x08 +dfii_command_cs = 0x01 +dfii_command_we = 0x02 +dfii_command_cas = 0x04 +dfii_command_ras = 0x08 dfii_command_wrdata = 0x10 dfii_command_rddata = 0x20 ddrx_mr1 = 0x6 init_sequence = [ - ("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000), - ("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000), - ("Load Mode Register 2, CWL=5", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), - ("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), - ("Load Mode Register 1", 6, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), - ("Load Mode Register 0, CL=6, BL=8", 2336, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200), - ("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200), + ("Release reset", 0, 0, dfii_control_odt | dfii_control_reset_n, 50000), + ( + "Bring CKE high", 0, 0, + dfii_control_cke | dfii_control_odt | dfii_control_reset_n, 10000), + ( + "Load Mode Register 2, CWL=5", 512, 2, dfii_command_ras + | dfii_command_cas | dfii_command_we | dfii_command_cs, 0), + ( + "Load Mode Register 3", 0, 3, dfii_command_ras | dfii_command_cas + | dfii_command_we | dfii_command_cs, 0), + ( + "Load Mode Register 1", 6, 1, dfii_command_ras | dfii_command_cas + | dfii_command_we | dfii_command_cs, 0), + ( + "Load Mode Register 0, CL=6, BL=8", 2336, 0, dfii_command_ras + | dfii_command_cas | dfii_command_we | dfii_command_cs, 200), + ("ZQ Calibration", 1024, 0, dfii_command_we | dfii_command_cs, 200), ] diff --git a/minitests/litex/uart_ddr/arty/scripts/test_sdram.py b/minitests/litex/uart_ddr/arty/scripts/test_sdram.py index 65358974..acee9d18 100755 --- a/minitests/litex/uart_ddr/arty/scripts/test_sdram.py +++ b/minitests/litex/uart_ddr/arty/scripts/test_sdram.py @@ -15,7 +15,7 @@ wb.open() # get identifier fpga_id = "" for i in range(256): - c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff) + c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff) fpga_id += c if c == "\0": break @@ -38,41 +38,51 @@ for i, (comment, a, ba, cmd, delay) in enumerate(init_sequence): # hardware control wb.regs.sdram_dfii_control.write(dfii_control_sel) + def seed_to_data(seed, random=True): if random: - return (1664525*seed + 1013904223) & 0xffffffff + return (1664525 * seed + 1013904223) & 0xffffffff else: return seed + def write_pattern(length): for i in range(length): - wb.write(wb.mems.main_ram.base + 4*i, seed_to_data(i)) + wb.write(wb.mems.main_ram.base + 4 * i, seed_to_data(i)) + def check_pattern(length, debug=False): errors = 0 for i in range(length): error = 0 - if wb.read(wb.mems.main_ram.base + 4*i) != seed_to_data(i): + if wb.read(wb.mems.main_ram.base + 4 * i) != seed_to_data(i): error = 1 if debug: - print("{}: 0x{:08x}, 0x{:08x} KO".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i))) + print( + "{}: 0x{:08x}, 0x{:08x} KO".format( + i, wb.read(wb.mems.main_ram.base + 4 * i), + seed_to_data(i))) else: if debug: - print("{}: 0x{:08x}, 0x{:08x} OK".format(i, wb.read(wb.mems.main_ram.base + 4*i), seed_to_data(i))) + print( + "{}: 0x{:08x}, 0x{:08x} OK".format( + i, wb.read(wb.mems.main_ram.base + 4 * i), + seed_to_data(i))) errors += error return errors + # find working bitslips and delays nbitslips = 8 -ndelays = 32 -nmodules = 2 -nwords = 16 +ndelays = 32 +nmodules = 2 +nwords = 16 for bitslip in range(nbitslips): print("bitslip {:d}: |".format(bitslip), end="") for delay in range(ndelays): for module in range(nmodules): - wb.regs.ddrphy_dly_sel.write(1<