From 858f50d9bbfed561495eb139e6f0377b3ce023d6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Jul 2017 09:57:10 +0200 Subject: [PATCH] Initial import Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- gridinfo/.gitignore | 8 ++++++ gridinfo/logicframes.tcl | 17 ++++++++++++ gridinfo/runme.sh | 56 ++++++++++++++++++++++++++++++++++++++++ gridinfo/tiledata.tcl | 16 ++++++++++++ settings.sh | 8 ++++++ 5 files changed, 105 insertions(+) create mode 100644 gridinfo/.gitignore create mode 100644 gridinfo/logicframes.tcl create mode 100644 gridinfo/runme.sh create mode 100644 gridinfo/tiledata.tcl create mode 100644 settings.sh diff --git a/gridinfo/.gitignore b/gridinfo/.gitignore new file mode 100644 index 00000000..d502a6c6 --- /dev/null +++ b/gridinfo/.gitignore @@ -0,0 +1,8 @@ +/.Xil +/design +/design.v +/design.xdc +/design.tcl +/design.log +/design.dcp +/logicframes_SLICE_*.bit diff --git a/gridinfo/logicframes.tcl b/gridinfo/logicframes.tcl new file mode 100644 index 00000000..81f25c32 --- /dev/null +++ b/gridinfo/logicframes.tcl @@ -0,0 +1,17 @@ + +set sites [get_sites -filter {(SITE_TYPE == "SLICEL" || SITE_TYPE == "SLICEM") && (NAME =~ "*Y0" || NAME =~ "*Y50" || NAME =~ "*Y?00" || NAME =~ "*Y?50")}] + +foreach site $sites { + puts ""; puts ""; puts ""; puts ""; puts ""; puts "" + puts "=========================== $site ===========================" + + set_property LOC $site [get_cells lut] + route_design + + set_property INIT 64'h8000000000000000 [get_cells lut] + write_bitstream -force logicframes_${site}_0.bit + + set_property INIT 64'h8000000000000001 [get_cells lut] + write_bitstream -force logicframes_${site}_1.bit +} + diff --git a/gridinfo/runme.sh b/gridinfo/runme.sh new file mode 100644 index 00000000..f9477521 --- /dev/null +++ b/gridinfo/runme.sh @@ -0,0 +1,56 @@ +#!/bin/bash + +set -ex + +source ../settings.sh + +cat > design.xdc << EOT +set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports I[0]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports I[1]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports I[2]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports I[3]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_04 IOSTANDARD LVCMOS33} [get_ports I[4]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_05 IOSTANDARD LVCMOS33} [get_ports I[5]] +set_property -dict {PACKAGE_PIN $XRAY_PIN_06 IOSTANDARD LVCMOS33} [get_ports O] + +set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} [get_cells lut] +set_property -dict {IS_LOC_FIXED 1 IS_BEL_FIXED 1 BEL SLICEL.A6LUT} [get_cells lut] + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] +EOT + +cat > design.v << EOT +module top(input [5:0] I, output O); + LUT6 #(.INIT(64'h8000000000000000)) lut ( + .I0(I[0]), + .I1(I[1]), + .I2(I[2]), + .I3(I[3]), + .I4(I[4]), + .I5(I[5]), + .O(O) + ); +endmodule +EOT + +cat > design.tcl << EOT +create_project -force -part $XRAY_PART design design + +read_xdc design.xdc +read_verilog design.v + +synth_design -top top +place_design +route_design + +write_checkpoint -force design.dcp + +source logicframes.tcl +source tiledata.tcl +EOT + +rm -f design.log +vivado -nojournal -log design.log -mode batch -source design.tcl + diff --git a/gridinfo/tiledata.tcl b/gridinfo/tiledata.tcl new file mode 100644 index 00000000..516644bd --- /dev/null +++ b/gridinfo/tiledata.tcl @@ -0,0 +1,16 @@ + +foreach tile [get_tiles] { + foreach prop [list_property $tile] { + puts "--tiledata-- TILEPROP $tile $prop [get_property $prop $tile]" + } + foreach site [get_sites -quiet -of_objects $tile] { + puts "--tiledata-- TILESITE $tile $site" + } +} + +foreach site [get_sites] { + foreach prop [list_property $site] { + puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]" + } +} + diff --git a/settings.sh b/settings.sh new file mode 100644 index 00000000..b1021a22 --- /dev/null +++ b/settings.sh @@ -0,0 +1,8 @@ +export XRAY_PART="xc7a50tfgg484-1" +export XRAY_PIN_00="E22" +export XRAY_PIN_01="D22" +export XRAY_PIN_02="E21" +export XRAY_PIN_03="D21" +export XRAY_PIN_04="G21" +export XRAY_PIN_05="G22" +export XRAY_PIN_06="F21"