diff --git a/experiments/clb_lut5/.gitignore b/experiments/clb_lut5/.gitignore
deleted file mode 100644
index ce77578f..00000000
--- a/experiments/clb_lut5/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/specimen_*/
-/*.segbits
diff --git a/experiments/clb_lut5/Makefile b/experiments/clb_lut5/Makefile
deleted file mode 100644
index 2d92fe6d..00000000
--- a/experiments/clb_lut5/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-N := 3
-SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
-SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
-
-database: $(SPECIMENS_OK)
-	${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
-
-pushdb:
-	${XRAY_MERGEDB} clbll_l seg_clblx.segbits
-	${XRAY_MERGEDB} clbll_r seg_clblx.segbits
-	${XRAY_MERGEDB} clblm_l seg_clblx.segbits
-	${XRAY_MERGEDB} clblm_r seg_clblx.segbits
-
-$(SPECIMENS_OK):
-	bash generate.sh $(subst /OK,,$@)
-	touch $@
-
-clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits
-
-.PHONY: database pushdb clean
-
diff --git a/experiments/clb_lut5/README.txt b/experiments/clb_lut5/README.txt
deleted file mode 100644
index 7807080f..00000000
--- a/experiments/clb_lut5/README.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Purpose:
-Understand LUT5 vs LUT6 configuration
-
-Algorithm:
-Generate a design with LUT6's and LUT6_2's (dual LUT5)
-Compare bitstream differences
-
-Outcome:
-Discovered an additional bit set when LUT6_2 is used
-
-
diff --git a/experiments/clb_lut5/generate.py b/experiments/clb_lut5/generate.py
deleted file mode 100644
index defbdae7..00000000
--- a/experiments/clb_lut5/generate.py
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/usr/bin/env python3
-
-import sys, re
-
-sys.path.append("../../../utils/")
-from segmaker import segmaker
-
-segmk = segmaker("design.bits")
-
-print("Loading tags from design.txt")
-with open("design.txt", "r") as f:
-    for line in f:
-        '''
-        puts $fp "$type $tile $grid_x $grid_y $lut $lut_type"
-        CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/B5LUT LUT5
-        CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/A6LUT LUT6
-        CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X12Y112/C6LUT LUT_OR_MEM6
-        CLBLM_L CLBLM_L_X10Y145 30 5 SLICE_X12Y145/D5LUT LUT_OR_MEM5
-
-        updated
-        CLBLM_L CLBLM_L_X10Y149 30 1 SLICE_X12Y149/C6LUT LUT_OR_MEM6 SLICEM.C6LUT
-        '''
-        line = line.split()
-        tile_type = line[0]
-        tile_name = line[1]
-        grid_x = line[2]
-        grid_y = line[3]
-        # Other code uses BEL name
-        site_lut_name = line[4]
-        site, lut_name = site_lut_name.split('/')
-        lut_type = line[5]
-        # SLICEL.A6LUT
-        cell_bel = line[6]
-        slicelm = cell_bel.split('.')[0]
-
-        which = lut_name[0]
-        is_lut5 = lut_type in ('LUT5', 'LUT_OR_MEM5')
-        site_mod = site + '.' + slicelm
-        site_mod = site
-        segmk.addtag(site, slicelm + '.' + "%cLUT5" % which, is_lut5)
-
-segmk.compile()
-segmk.write()
-
diff --git a/experiments/clb_lut5/generate.sh b/experiments/clb_lut5/generate.sh
deleted file mode 100644
index cb2ea03f..00000000
--- a/experiments/clb_lut5/generate.sh
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/bin/bash
-
-source ${XRAY_GENHEADER}
-
-echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
-
-vivado -mode batch -source ../generate.tcl
-
-for x in design*.bit; do
-	${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
-done
-
-python3 ../generate.py
-
diff --git a/experiments/clb_lut5/generate.tcl b/experiments/clb_lut5/generate.tcl
deleted file mode 100644
index cc543186..00000000
--- a/experiments/clb_lut5/generate.tcl
+++ /dev/null
@@ -1,64 +0,0 @@
-create_project -force -part $::env(XRAY_PART) design design
-
-read_verilog ../top.v
-synth_design -top top
-
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
-
-create_pblock roi
-add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
-
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
-
-place_design
-route_design
-
-write_checkpoint -force design.dcp
-write_bitstream -force design.bit
-
-
-# Get all 6LUT and 5LUT in pblock
-# A6LUT, B6LUT, A5LUT, etc
-set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */*LUT]
-
-set grid_min_x -1
-set grid_max_x -1
-set grid_min_y -1
-set grid_max_y -1
-
-foreach lut $luts {
-	set tile [get_tile -of_objects $lut]
-	set grid_x [get_property GRID_POINT_X $tile]
-	set grid_y [get_property GRID_POINT_Y $tile]
-
-	if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
-	if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
-
-	if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
-	if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
-}
-
-set fp [open "design.txt" w]
-foreach lut $luts {
-	if [get_property IS_USED $lut] {
-	    set tile [get_tile -of_objects $lut]
-	    set grid_x [get_property GRID_POINT_X $tile]
-	    set grid_y [get_property GRID_POINT_Y $tile]
-	    set type [get_property TYPE $tile]
-	    set lut_type [get_property TYPE $lut]
-	    set lutc [get_cells -of_objects $lut]
-	    set cell_bel [get_property BEL $lutc]
-
-		puts $fp "$type $tile $grid_x $grid_y $lut $lut_type $cell_bel"
-	}
-}
-close $fp
-
diff --git a/experiments/clb_lut5/top.v b/experiments/clb_lut5/top.v
deleted file mode 100644
index d73ba5d4..00000000
--- a/experiments/clb_lut5/top.v
+++ /dev/null
@@ -1,112 +0,0 @@
-`include "setseed.vh"
-
-`define N 1000
-
-module top(input clk, stb, di, output do);
-	localparam integer DIN_N = 6;
-	localparam integer DOUT_N = `N;
-
-	reg [DIN_N-1:0] din;
-	wire [DOUT_N-1:0] dout;
-
-	reg [DIN_N-1:0] din_shr;
-	reg [DOUT_N-1:0] dout_shr;
-
-	always @(posedge clk) begin
-		din_shr <= {din_shr, di};
-		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
-		if (stb) begin
-			din <= din_shr;
-			dout_shr <= dout;
-		end
-	end
-
-	assign do = dout_shr[DOUT_N-1];
-
-	roi roi (
-		.clk(clk),
-		.din(din),
-		.dout(dout)
-	);
-endmodule
-
-module roi(input clk, input [5:0] din, output [`N-1:0] dout);
-	function [31:0] xorshift32(input [31:0] v);
-		begin
-			xorshift32 = v;
-			xorshift32 = xorshift32 ^ (xorshift32 << 13);
-			xorshift32 = xorshift32 ^ (xorshift32 >> 17);
-			xorshift32 = xorshift32 ^ (xorshift32 <<  5);
-		end
-	endfunction
-
-	function [31:0] hash32(input [31:0] v);
-		begin
-			hash32 = v ^ `SEED;
-			hash32 = xorshift32(hash32);
-			hash32 = xorshift32(hash32);
-			hash32 = xorshift32(hash32);
-			hash32 = xorshift32(hash32);
-		end
-	endfunction
-
-	function [63:0] hash64(input [31:0] v);
-		begin
-			hash64[63:32] = hash32(v);
-			hash64[31: 0] = hash32(~v);
-		end
-	endfunction
-
-	genvar i;
-	generate
-		for (i = 0; i < `N; i = i+1) begin:is
-			/*
-		    wire o5;
-		    wire o6;
-		    assign dout[i] = o5 & o6;
-			LUT5 #(
-				.INIT(32'h8000_0001 + (i << 16) + 1'b1)
-			) lut5 (
-				.I0(din[0]),
-				.I1(din[f1]),
-				.I2(din[2]),
-				.I3(din[3]),
-				.I4(din[4]),
-				.O(o5)
-			);
-			*/
-
-			wire o6;
-			wire o2_5;
-			wire o2_6;
-			//Randomly take out 1/4 iterations
-			wire [3:0] hash = hash32(i);
-			wire opt_out = |hash;
-			assign dout[i] = o6 & o2_5 & o2_6 & opt_out;
-
-			LUT6 #(
-				.INIT(64'h8000_0000_0000_0001 + (i << 16))
-			) lut6 (
-				.I0(din[0]),
-				.I1(din[1]),
-				.I2(din[2]),
-				.I3(din[3]),
-				.I4(din[4]),
-				.I5(din[5]),
-				.O(o6)
-			);
-			LUT6_2 #(
-				.INIT(64'h8000_0000_0000_0001 + (i << 8))
-			) lut62 (
-				.I0(din[0]),
-				.I1(din[1]),
-				.I2(din[2]),
-				.I3(din[3]),
-				.I4(din[4]),
-				.I5(din[5]),
-				.O5(o2_5),
-				.O6(o2_6)
-			);
-		end
-	endgenerate
-endmodule