From 85060dd1d64b3d223509975134c66f5008d320dd Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 28 Apr 2019 19:01:58 -0700 Subject: [PATCH] Fix the INT references. Signed-off-by: Tim 'mithro' Ansell --- docs/architecture/interconnect.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/architecture/interconnect.rst b/docs/architecture/interconnect.rst index f6070750..87ef675f 100644 --- a/docs/architecture/interconnect.rst +++ b/docs/architecture/interconnect.rst @@ -8,7 +8,7 @@ Some :term:`PIPs ` are not "real", in the sense that no bit pattern in the .. warning:: FIXME: Check the above is true. -The bit switchbox in an :term:`INT`s tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits. +The bit switchbox in an :term:`INTs ` tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits. Regular :term:`PIPs ` -------------------------- @@ -17,7 +17,7 @@ Regular :term:`PIPs ` correspond to a bit pattern that is present in the bi .. warning:: FIXME: Check if the above is true for PIPs outside of the INT switch box. -For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L`s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs `. +For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L `s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs `. VCC Drivers -----------