From 804af47dc550ec8e1379ce09506c3bf186148211 Mon Sep 17 00:00:00 2001 From: Dr Jonathan Richard Robert Kimmitt Date: Fri, 29 May 2026 11:10:05 +0100 Subject: [PATCH] README: link the Virtex-7 section from the top Add a callout under the project tagline pointing Virtex-7 / VC707 users straight to the Virtex-7 Port Status section, and note that the Quickstart Guide assumes the upstream Artix-7 / 2017.2 path. Co-Authored-By: Claude Opus 4.7 --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index 2ec930aa..2ccbd61d 100644 --- a/README.md +++ b/README.md @@ -9,6 +9,12 @@ Documenting the Xilinx 7-series bit-stream format. This repository contains both tools and scripts which allow you to document the bit-stream format of Xilinx 7-series FPGAs. +> **Virtex-7 / VC707 users:** see [**Virtex-7 Port +> Status**](#virtex-7-port-status-virtex7-support-branch) below for the +> `virtex7-support` branch — different Vivado version, working open flow +> on `xc7vx485tffg1761-2`, and device-specific patches. The Quickstart +> Guide that follows assumes the upstream Artix-7 / 2017.2 path. + More documentation can be found published on [prjxray ReadTheDocs site](https://prjxray.readthedocs.io/en/latest/) - this includes; * [Highlevel Bitstream Architecture](https://prjxray.readthedocs.io/en/latest/architecture/overview.html) * [Overview of DB Development Process](https://prjxray.readthedocs.io/en/latest/db_dev_process/index.html)