From 7f2fa3f801c3651acc958a62bdb41777dbad3cf5 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 30 Jan 2019 16:50:34 -0800 Subject: [PATCH] Add more zero bits, and fix address emission. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/060-bram-cascades/bits.dbf | 16 ++++++++++++++++ fuzzers/060-bram-cascades/top.py | 13 ++++++++----- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/fuzzers/060-bram-cascades/bits.dbf b/fuzzers/060-bram-cascades/bits.dbf index 3b37454a..9115a980 100644 --- a/fuzzers/060-bram-cascades/bits.dbf +++ b/fuzzers/060-bram-cascades/bits.dbf @@ -1,6 +1,13 @@ +26_160 26_161 26_163,BRAM.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6 +26_176 26_177 26_179,BRAM.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7 +26_80 26_81 26_83 ,BRAM.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 + 26_184 26_185 26_187,BRAM.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 26_88 26_89 26_91 ,BRAM.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 +26_37 26_38 26_39 ,BRAM.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 +26_53 26_54 26_55 ,BRAM.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 +26_69 26_70 26_71 ,BRAM.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 26_197 26_198 26_199,BRAM.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 26_101 26_102 26_103,BRAM.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 26_229 26_230 26_231,BRAM.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 @@ -8,14 +15,18 @@ 26_181 26_182 26_183,BRAM.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 26_85 26_86 26_87 ,BRAM.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 26_213 26_214 26_215,BRAM.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 +26_149 26_150 26_151,BRAM.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 26_77 26_78 26_79 ,BRAM.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 26_205 26_206 26_207,BRAM.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 +26_109 26_110 26_111,BRAM.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 26_237 26_238 26_239,BRAM.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 26_173 26_174 26_175,BRAM.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 26_189 26_190 26_191,BRAM.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 26_93 26_94 26_95 ,BRAM.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 26_221 26_222 26_223,BRAM.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 +26_157 26_158 26_159,BRAM.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 +26_125 26_126 26_127,BRAM.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 26_176 26_177 26_179,BRAM.BRAM_ADDRARDADDRL7.BRAM_R_IMUX_ADDRARDADDRL7 26_80 26_81 26_83 ,BRAM.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 @@ -24,7 +35,12 @@ 26_181 26_182 26_183,BRAM.BRAM_ADDRARDADDRU7.BRAM_R_IMUX_ADDRARDADDRU7 26_85 26_86 26_87 ,BRAM.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 +26_168 26_169 26_171,BRAM.BRAM_ADDRBWRADDRL6.BRAM_R_IMUX_ADDRBWRADDRL6 +26_184 26_185 26_187,BRAM.BRAM_ADDRBWRADDRL7.BRAM_R_IMUX_ADDRBWRADDRL7 26_88 26_89 26_91 ,BRAM.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 +26_109 26_110 26_111,BRAM.BRAM_ADDRBWRADDRU4.BRAM_R_IMUX_ADDRBWRADDRU4 +26_237 26_238 26_239,BRAM.BRAM_ADDRBWRADDRU5.BRAM_R_IMUX_ADDRBWRADDRU5 +26_173 26_174 26_175,BRAM.BRAM_ADDRBWRADDRU6.BRAM_R_IMUX_ADDRBWRADDRU6 26_189 26_190 26_191,BRAM.BRAM_ADDRBWRADDRU7.BRAM_R_IMUX_ADDRBWRADDRU7 26_93 26_94 26_95 ,BRAM.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 diff --git a/fuzzers/060-bram-cascades/top.py b/fuzzers/060-bram-cascades/top.py index c77b4ee6..f741004a 100644 --- a/fuzzers/060-bram-cascades/top.py +++ b/fuzzers/060-bram-cascades/top.py @@ -111,18 +111,21 @@ def emit_sdp_bram(luts, name, modules, lines, width, address_bits): modules.append(sdp_bram(name=name, width=width, address_bits=address_bits)) lines.append(''' - wire [9:0] {name}_wraddr; - wire [9:0] {name}_rdaddr; - '''.format(name=name)) + wire [{address_bits}-1:0] {name}_wraddr; + wire [{address_bits}-1:0] {name}_rdaddr; + '''.format( + name=name, + address_bits=address_bits, + )) - for bit in range(10): + for bit in range(address_bits): lines.append(""" assign {name}_wraddr[{bit}] = {net};""".format( name=name, bit=bit, net=luts.get_next_output_net())) - for bit in range(10): + for bit in range(address_bits): lines.append(""" assign {name}_rdaddr[{bit}] = {net};""".format( name=name,