From 7bae4bbddbe3a895f1e6044857e09ccb4f73cceb Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 15 Oct 2018 15:09:21 -0700 Subject: [PATCH] bram minitest: build all projects Signed-off-by: John McMaster --- minitests/bram_basic/Makefile | 39 +++++++++- minitests/bram_basic/runme.sh | 18 +++++ minitests/bram_basic/runme.tcl | 29 +++++++ minitests/bram_basic/top.v | 133 +++++++++++++++++++++++++-------- 4 files changed, 187 insertions(+), 32 deletions(-) create mode 100644 minitests/bram_basic/runme.sh create mode 100644 minitests/bram_basic/runme.tcl diff --git a/minitests/bram_basic/Makefile b/minitests/bram_basic/Makefile index 1d13e215..7a1166c7 100644 --- a/minitests/bram_basic/Makefile +++ b/minitests/bram_basic/Makefile @@ -1 +1,38 @@ -include ../util/common.mk +all: build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff + +clean: + rm -rf build + + +# Toggle all bits in a single BRAM data section +build/roi_bramd_bits01.diff: build/roi_bramd_bits0/design.bits build/roi_bramd_bits1/design.bits + diff build/roi_bramd_bits{0,1}/design.bits >build/roi_bramd_bits01.diff || true + +build/roi_bramd_bits0/design.bits: + PROJECT=roi_bramd_bits0 bash runme.sh + +build/roi_bramd_bits1/design.bits: + PROJECT=roi_bramd_bits1 bash runme.sh + + +# Toggle one bit in each BRAM data section +build/roi_bramds_bit01.diff: build/roi_bramds_bit0/design.bits build/roi_bramds_bit1/design.bits + diff build/roi_bramds_bit{0,1}/design.bits >build/roi_bramds_bit01.diff || true + +build/roi_bramds_bit0/design.bits: + PROJECT=roi_bramds_bit0 bash runme.sh + +build/roi_bramds_bit1/design.bits: + PROJECT=roi_bramds_bit1 bash runme.sh + + +# Toggle one bit in each BRAM config section +build/roi_bramis_bit01.diff: build/roi_bramis_bit0/design.bits build/roi_bramis_bit1/design.bits + diff build/roi_bramis_bit{0,1}/design.bits >build/roi_bramis_bit01.diff || true + +build/roi_bramis_bit0/design.bits: + PROJECT=roi_bramis_bit0 bash runme.sh + +build/roi_bramis_bit1/design.bits: + PROJECT=roi_bramis_bit1 bash runme.sh + diff --git a/minitests/bram_basic/runme.sh b/minitests/bram_basic/runme.sh new file mode 100644 index 00000000..9390d5ff --- /dev/null +++ b/minitests/bram_basic/runme.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -ex + +: "${PROJECT:?Need to set PROJECT non-empty}" + +# Create build dir +export SRC_DIR=$PWD +BUILD_DIR=build/$PROJECT +mkdir -p $BUILD_DIR +cd $BUILD_DIR + +export TOP_V=$SRC_DIR/top.v + +vivado -mode batch -source $SRC_DIR/runme.tcl +${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit +test -z "$(fgrep CRITICAL vivado.log)" + diff --git a/minitests/bram_basic/runme.tcl b/minitests/bram_basic/runme.tcl new file mode 100644 index 00000000..9674265d --- /dev/null +++ b/minitests/bram_basic/runme.tcl @@ -0,0 +1,29 @@ +create_project -force -part $::env(XRAY_PART) design design +#read_verilog $::env(SRC_DIR)/$::env(PROJECT).v +read_verilog $::env(TOP_V) +synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT) + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp + +# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design] +write_bitstream -force design.bit + diff --git a/minitests/bram_basic/top.v b/minitests/bram_basic/top.v index c346f647..69a934f6 100644 --- a/minitests/bram_basic/top.v +++ b/minitests/bram_basic/top.v @@ -6,7 +6,7 @@ ROM64X1: 64-Deep by 1-Wide ROM */ `ifndef ROI -`define ROI +ERROR: must set ROI `endif module top(input clk, stb, di, output do); @@ -30,16 +30,7 @@ module top(input clk, stb, di, output do); assign do = dout_shr[DOUT_N-1]; - //`ROI - - //sweep through these three values to see small config vs data changes - //roi_bram0 - //roi_bram1 - //roi_bram_inv - - //sweep through to see all data bits toggle to get idea of size - //roi_bram36_0s - roi_bram36_1s + `ROI roi ( .clk(clk), .din(din), @@ -47,43 +38,99 @@ module top(input clk, stb, di, output do); ); endmodule -//HCK test -//XXX: what specifically was this testing? -module roi_hck(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT({256{1'b1}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT({256{1'b1}})) - r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - //HCK - ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT({256{1'b1}})) - r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT({256{1'b1}})) - r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); -endmodule +/****************************************************************************** +DATA ROI +******************************************************************************/ -/* -One BRAM per tile -*/ -module roi_bram0(input clk, input [255:0] din, output [255:0] dout); +/****************************************************************************** +Toggle a single data bit to locate a single instance +******************************************************************************/ +module roi_bramd_bit0(input clk, input [255:0] din, output [255:0] dout); ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule -module roi_bram1(input clk, input [255:0] din, output [255:0] dout); +module roi_bramd_bit1(input clk, input [255:0] din, output [255:0] dout); ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}})) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule +/****************************************************************************** +Toggle all bits to show the size of the data section +******************************************************************************/ +module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +/****************************************************************************** +Toggle all the data bits in the ROI to show pitch between entries +******************************************************************************/ +module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}})) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}})) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}})) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}})) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}})) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}})) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}})) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}})) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}})) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b1), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b1), .INIT({256{1'b0}})) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b1), .INIT({256{1'b0}})) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b1), .INIT({256{1'b0}})) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b1), .INIT({256{1'b0}})) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b1), .INIT({256{1'b0}})) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b1), .INIT({256{1'b0}})) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b1), .INIT({256{1'b0}})) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b1), .INIT({256{1'b0}})) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b1), .INIT({256{1'b0}})) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +/****************************************************************************** +CONFIG ROI +******************************************************************************/ + //ram_RAMB36E1 too much churn to be useful to compare vs above //instead lets change something more subtle // ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND: roi/r0/ram programming // per UG473 requires that for SDP mode the WEA bus must be unconnected or tied to GND. -module roi_bram_sdp(input clk, input [255:0] din, output [255:0] dout); +module roi_bramd_sdp(input clk, input [255:0] din, output [255:0] dout); ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .RAM_MODE("SDP")) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule -module roi_bram_inv(input clk, input [255:0] din, output [255:0] dout); +module roi_bramd_inv(input clk, input [255:0] din, output [255:0] dout); ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1)) r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule @@ -137,6 +184,30 @@ module roi_invalid(input clk, input [255:0] din, output [255:0] dout); r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); endmodule +/****************************************************************************** +Misc ROI +******************************************************************************/ + +//HCK test +//XXX: what specifically was this testing? +module roi_hck(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT({256{1'b1}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT({256{1'b1}})) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + //HCK + ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT({256{1'b1}})) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT({256{1'b1}})) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + +endmodule + +/****************************************************************************** +Library +******************************************************************************/ + + /* Site RAMB18_X0Y42 Pushed it outside the pblock