From 79d6b330e70ea85c22874593bdd8a7035a309ff4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Dec 2017 17:04:46 +0000 Subject: [PATCH] Add hclk buffer enable bits Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- database/artix7/ppips_hclk_l.txt | 8 ++++++++ database/artix7/ppips_hclk_r.txt | 8 ++++++++ fuzzers/058-hclkpips/.gitignore | 1 + fuzzers/058-hclkpips/Makefile | 6 +++++- fuzzers/058-hclkpips/generate.py | 17 +++++++++++++---- 5 files changed, 35 insertions(+), 5 deletions(-) create mode 100644 database/artix7/ppips_hclk_l.txt create mode 100644 database/artix7/ppips_hclk_r.txt diff --git a/database/artix7/ppips_hclk_l.txt b/database/artix7/ppips_hclk_l.txt new file mode 100644 index 00000000..6959965e --- /dev/null +++ b/database/artix7/ppips_hclk_l.txt @@ -0,0 +1,8 @@ +HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always +HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always +HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always +HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always +HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always +HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always +HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always +HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always diff --git a/database/artix7/ppips_hclk_r.txt b/database/artix7/ppips_hclk_r.txt new file mode 100644 index 00000000..45231f33 --- /dev/null +++ b/database/artix7/ppips_hclk_r.txt @@ -0,0 +1,8 @@ +HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always +HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always +HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always +HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always +HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always +HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always +HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always +HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always diff --git a/fuzzers/058-hclkpips/.gitignore b/fuzzers/058-hclkpips/.gitignore index cfb168a7..83e2d310 100644 --- a/fuzzers/058-hclkpips/.gitignore +++ b/fuzzers/058-hclkpips/.gitignore @@ -1,3 +1,4 @@ /specimen_*/ /seg_hclk_[lr].segbits /mask_hclk_[lr].segbits +/ppips_hclk_[lr].txt diff --git a/fuzzers/058-hclkpips/Makefile b/fuzzers/058-hclkpips/Makefile index 5099f781..fdd56c79 100644 --- a/fuzzers/058-hclkpips/Makefile +++ b/fuzzers/058-hclkpips/Makefile @@ -8,12 +8,16 @@ database: $(SPECIMENS_OK) ${XRAY_SEGMATCH} -o seg_hclk_r.segbits $(addsuffix /segdata_hclk_r_design_*.txt,$(SPECIMENS)) ${XRAY_MASKMERGE} mask_hclk_l.segbits $(addsuffix /segdata_hclk_l_design_*.txt,$(SPECIMENS)) ${XRAY_MASKMERGE} mask_hclk_r.segbits $(addsuffix /segdata_hclk_r_design_*.txt,$(SPECIMENS)) + grep CK_INOUT seg_hclk_l.segbits | sed 's, .*, always,' > ppips_hclk_l.txt + grep CK_INOUT seg_hclk_r.segbits | sed 's, .*, always,' > ppips_hclk_r.txt pushdb: ${XRAY_MERGEDB} hclk_l seg_hclk_l.segbits ${XRAY_MERGEDB} hclk_r seg_hclk_r.segbits ${XRAY_MERGEDB} mask_hclk_l mask_hclk_l.segbits ${XRAY_MERGEDB} mask_hclk_r mask_hclk_r.segbits + cp ppips_hclk_l.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ + cp ppips_hclk_r.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ ${XRAY_DBFIXUP} $(SPECIMENS_OK): @@ -21,7 +25,7 @@ $(SPECIMENS_OK): touch $@ clean: - rm -rf specimen_[0-9][0-9][0-9]/ seg_hclk_[lr].segbits mask_hclk_[lr].segbits + rm -rf specimen_[0-9][0-9][0-9]/ seg_hclk_[lr].segbits mask_hclk_[lr].segbits ppips_hclk_[lr].txt .PHONY: database pushdb clean diff --git a/fuzzers/058-hclkpips/generate.py b/fuzzers/058-hclkpips/generate.py index c0dba5e3..a3d8fead 100644 --- a/fuzzers/058-hclkpips/generate.py +++ b/fuzzers/058-hclkpips/generate.py @@ -6,6 +6,7 @@ sys.path.append("../../../utils/") from segmaker import segmaker tags = dict() +en_tags = dict() print("Preload all tags.") for arg in sys.argv[1:]: @@ -16,7 +17,10 @@ for arg in sys.argv[1:]: tile_type, pip = pip.split(".") src, dst = pip.split("->>") tag = "%s.%s" % (dst, src) - tags[tag] = (dst, src) + tags[tag] = dst + if "HCLK_CK_BUFH" in src: + en_tag = "ENABLE_BUFFER.%s" % src + en_tags[en_tag] = src for arg in sys.argv[1:]: print("Processing %s." % arg) @@ -34,10 +38,15 @@ for arg in sys.argv[1:]: src, dst = pip.split("->>") tag = "%s.%s" % (dst, src) segmk.addtag(tile, tag, 1) - for tag, tag_dst_src in tags.items(): - tag_dst, tag_src = tag_dst_src - if tag_dst != dst and (tag_src != src or True): + if "HCLK_CK_BUFH" in src: + en_tag = "ENABLE_BUFFER.%s" % src + segmk.addtag(tile, en_tag, 1) + for tag, tag_dst in tags.items(): + if tag_dst != dst: segmk.addtag(tile, tag, 0) + for en_tag, en_tag_src in en_tags.items(): + if en_tag_src != src: + segmk.addtag(tile, en_tag, 0) segmk.compile() segmk.write(arg)