From 75e9a2acd911a23c8769fcd2de4fb80dd28b4c49 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 26 Feb 2019 19:32:24 -0800 Subject: [PATCH] Fix the output of internal routing MUXs in the CLBs. Before; ``` CLBLL_L.SLICEL_X1.A5FFMUX Bit Name Position CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08 CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11 ``` After; ``` PIPs driving CLBLL_L.SLICEL_X0.B5FFMUX PIP 30_18 30_19 CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 1 - CLBLL_L.SLICEL_X0.B5FFMUX.IN_A - 1 ``` Signed-off-by: Tim 'mithro' Ansell --- htmlgen/htmlgen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/htmlgen/htmlgen.py b/htmlgen/htmlgen.py index 4d835763..2ec3b181 100755 --- a/htmlgen/htmlgen.py +++ b/htmlgen/htmlgen.py @@ -110,7 +110,7 @@ def db_read(dbstate, tiletype, db_dir): add_pip_bits(tag, bits) elif tiletype in ["clbll_l", "clbll_r", "clblm_l", "clblm_r"] and \ - re.search(r"(\.[ABCD]MUX\.)|(\.PRECYINIT\.)", tag): + re.search(r"(\.[ABCD].*MUX\.)|(\.PRECYINIT\.)", tag): add_pip_bits(tag, bits) else: