From 73979fdf04104d877de63395554b40e246eb7299 Mon Sep 17 00:00:00 2001
From: Karol Gugala <kgugala@antmicro.com>
Date: Tue, 4 Jun 2019 20:31:59 +0200
Subject: [PATCH] fuzzers: 007: handle pin/pin and pin/prop aliases

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
---
 fuzzers/007-timing/bel/pin_alias_map.json | 56 ++++++++++++++++++++++-
 fuzzers/007-timing/bel/tim2json.py        | 14 +++---
 2 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/fuzzers/007-timing/bel/pin_alias_map.json b/fuzzers/007-timing/bel/pin_alias_map.json
index 3b130372..02465c83 100644
--- a/fuzzers/007-timing/bel/pin_alias_map.json
+++ b/fuzzers/007-timing/bel/pin_alias_map.json
@@ -1,8 +1,60 @@
 {
     "ff_init": {
-        "Q": ["QL", "QH"]
+        "Q": {
+             "names" : ["QL", "QH"],
+             "property" : true
+         }
     },
     "reg_init": {
-        "Q": ["QL", "QH"]
+        "Q": {
+             "names" : ["QL", "QH"],
+             "property" : true
+         }
+    },
+    "rambfifo36e1" : {
+         "RSTRAMARSTRAMLRST" : {
+             "names" : ["rstramarstl"],
+             "property" : false
+         },
+         "ADDRARDADDRU0" : {
+             "names" : ["addrau"],
+             "property" : false
+         },
+         "ADDRARDADDRL15" : {
+             "names" : ["addra15l"],
+             "property" : false
+         },
+         "RSTRAMARSTRAMU" : {
+             "names" : ["rstramau"],
+             "property" : false
+         },
+         "ADDRBWRADDRU0" : {
+             "names" : ["addrbu"],
+             "property" : false
+         },
+         "ADDRBWRADDRL15" : {
+             "names" : ["addrb15l"],
+             "property" : false
+         },
+         "WEBWEU0" : {
+             "names" : ["webu"],
+             "property" : false
+         },
+         "DOADO0" : {
+             "names" : ["doadol", "doadou"],
+             "property" : false
+         },
+         "DOBDO0" : {
+             "names" : ["dobdol", "dobdou"],
+             "property" : false
+         },
+         "DOPADOP0" : {
+             "names" : ["dopadopl", "dopadopu"],
+             "property" : false
+         },
+         "DOPBDOP0" : {
+             "names" : ["dopbdopl", "dopbdopu"],
+             "property" : false
+         }
     }
 }
diff --git a/fuzzers/007-timing/bel/tim2json.py b/fuzzers/007-timing/bel/tim2json.py
index c82d3eee..073dc497 100644
--- a/fuzzers/007-timing/bel/tim2json.py
+++ b/fuzzers/007-timing/bel/tim2json.py
@@ -93,11 +93,14 @@ def pin_in_model(pin, pin_aliases, model, direction=None):
             return True, pin
         elif extended_pin_name in model.split('_'):
             return True, extended_pin_name
-        elif pin_aliases is not None:
-            for alias in pin_aliases.get(pin.upper(), ()):
+        elif (pin_aliases is not None) and (pin.upper() in pin_aliases):
+            for alias in pin_aliases[pin.upper()]['names']:
                 pin_alias = alias.lower()
                 if pin_alias in model.split('_'):
-                    return True, pin
+                    if pin_aliases[pin.upper()]['property']:
+                        return True, pin
+                    else:
+                        return True, pin_alias
             return False, None
         else:
             return False, None
@@ -335,11 +338,6 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
                         # if we still don't have input, give up
                         if bel_input is None:
                             delay_loc += 6
-                            if slice.startswith('BRAM'):
-                                print("skipping BRAM for bel:", speed_model_orig)
-                                print("delay_btype_orig:", delay_btype_orig)
-                                print("btype:", btype)
-                            continue
 
                         # restore speed model name
                         speed_model = delay_btype + speed_model_clean