From 716e4ca78534bd5ffa56106edec10fa40da6648f Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 30 Jul 2019 08:33:18 -0700
Subject: [PATCH] Add ISERDESE2.DATA_WIDTH's 2-8.

10 and 14 require ISERDESE2 MASTER/SLAVE which are not currently in use.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/035-iob-ilogic/bits.dbf    |  2 ++
 fuzzers/035-iob-ilogic/generate.py | 40 ++++++++++++++++++++++++++----
 fuzzers/035-iob-ilogic/top.py      |  1 +
 3 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/fuzzers/035-iob-ilogic/bits.dbf b/fuzzers/035-iob-ilogic/bits.dbf
index e69de29b..37275398 100644
--- a/fuzzers/035-iob-ilogic/bits.dbf
+++ b/fuzzers/035-iob-ilogic/bits.dbf
@@ -0,0 +1,2 @@
+27_110 27_112 26_109 ,IOB33.IOB_Y0.ISERDES.DATA_WIDTH.W2
+26_15  26_17  27_18  ,IOB33.IOB_Y1.ISERDES.DATA_WIDTH.W2
diff --git a/fuzzers/035-iob-ilogic/generate.py b/fuzzers/035-iob-ilogic/generate.py
index 9fbb4b45..363a22e3 100644
--- a/fuzzers/035-iob-ilogic/generate.py
+++ b/fuzzers/035-iob-ilogic/generate.py
@@ -19,13 +19,43 @@ def handle_data_width(segmk, d):
     if 'DATA_WIDTH' not in d:
         return
 
-    if d['DATA_RATE'] == 'DDR':
-        return
+    # It appears several widths end up with the same bitstream pattern.
+    # This groups those widths together for documentation.
+    widths = [
+        [2],
+        [3],
+        [4, 6],
+        [5, 7],
+        [8],
+        [10],
+        [14],
+    ]
 
-    for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
+    width_map = {}
+
+    for ws in widths:
+        for w in ws:
+            width_map[w] = 'W{}'.format('_'.join(map(str, ws)))
+
+    zero_opt = 2
+    W_OPT_ZERO = width_map[zero_opt]
+    if d['DATA_WIDTH'] == zero_opt:
         segmk.add_site_tag(
-            d['site'], 'ISERDES.DATA_WIDTH.W{}'.format(opt),
-            d['DATA_WIDTH'] == opt)
+            d['site'], 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 1)
+
+        for opt in width_map.values():
+            if opt == W_OPT_ZERO:
+                continue
+
+            segmk.add_site_tag(
+                d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt), 0)
+    else:
+        w_opt = width_map[d['DATA_WIDTH']]
+        if w_opt != W_OPT_ZERO:
+            segmk.add_site_tag(
+                d['site'], 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 0)
+            segmk.add_site_tag(
+                d['site'], 'ISERDES.DATA_WIDTH.{}'.format(w_opt), 1)
 
 
 def handle_data_rate(segmk, d):
diff --git a/fuzzers/035-iob-ilogic/top.py b/fuzzers/035-iob-ilogic/top.py
index b54f0f62..70de3566 100644
--- a/fuzzers/035-iob-ilogic/top.py
+++ b/fuzzers/035-iob-ilogic/top.py
@@ -221,6 +221,7 @@ def use_iserdese2(p, luts, connects):
         .OFB_USED({OFB_USED}),
         .NUM_CE({NUM_CE}),
         .DATA_RATE({DATA_RATE}),
+        .DATA_WIDTH({DATA_WIDTH}),
         .IOBDELAY({IOBDELAY})
     ) iserdese2_{site} (
         {ddly_connection}