diff --git a/fuzzers/062-pcie-int-pips/Makefile b/fuzzers/062-pcie-int-pips/Makefile
new file mode 100644
index 00000000..e74ea835
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/Makefile
@@ -0,0 +1,60 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+export FUZDIR=$(shell pwd)
+PIP_TYPE?=pcie_int_interface
+SEG_TYPE?=pcie_int_interface
+PIPLIST_TCL=$(FUZDIR)/pcie_int_interface_pip_list.tcl
+
+BUILD_DIR = build
+RUN_OK = run.ok
+
+TODO_RE=".*"
+
+MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(SEG_TYPE) --re $(TODO_RE) --sides "l,r"
+N = 5
+
+SEGMATCH_FLAGS=-c 1
+
+A_PIPLIST=pcie_int_interface_l.txt
+
+CHECK_ARGS= --zero-entries --min-iters 1 --max-iters 2
+
+include ../pip_loop.mk
+
+$(BUILD_DIR)/segbits_pcie_int_interface.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb \
+		$(shell find $(BUILD_DIR) -name segdata_pcie_int_interface_l.txt)
+	${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb \
+		$(shell find $(BUILD_DIR) -name segdata_pcie_int_interface_r.txt)
+
+RDBS = $(BUILD_DIR)/segbits_pcie_int_interface.rdb
+
+database: ${RDBS}
+	${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
+		--seg-fn-in $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb \
+		--seg-fn-out $(BUILD_DIR)/segbits_pcie_int_interface_l.db
+	${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
+		--seg-fn-in $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb \
+		--seg-fn-out $(BUILD_DIR)/segbits_pcie_int_interface_r.db
+
+	# Keep a copy to track iter progress
+	cp $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_l.rdb
+	cp $(BUILD_DIR)/segbits_pcie_int_interface_l.db $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_l.db
+	cp $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_r.rdb
+	cp $(BUILD_DIR)/segbits_pcie_int_interface_r.db $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_r.db
+
+	# Clobber existing .db to eliminate potential conflicts
+	cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE}
+	XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} pcie_int_interface_l $(BUILD_DIR)/segbits_pcie_int_interface_l.db
+	XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} pcie_int_interface_r $(BUILD_DIR)/segbits_pcie_int_interface_r.db
+
+pushdb: database
+	${XRAY_MERGEDB} pcie_int_interface_l $(BUILD_DIR)/segbits_pcie_int_interface_l.db
+	${XRAY_MERGEDB} pcie_int_interface_r $(BUILD_DIR)/segbits_pcie_int_interface_r.db
+
+.PHONY: database pushdb run clean
diff --git a/fuzzers/062-pcie-int-pips/bits.dbf b/fuzzers/062-pcie-int-pips/bits.dbf
new file mode 100644
index 00000000..e69de29b
diff --git a/fuzzers/062-pcie-int-pips/generate.py b/fuzzers/062-pcie-int-pips/generate.py
new file mode 100644
index 00000000..510c1817
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/generate.py
@@ -0,0 +1,98 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+from prjxray.segmaker import Segmaker
+import os
+import os.path
+
+
+def bitfilter(frame, word):
+    if frame not in [26, 27]:
+        return False
+
+    return True
+
+
+def read_pip_data(pipfile, pipdata, tile_ports):
+    with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
+                           'pcie_int_interface', pipfile)) as f:
+        for l in f:
+            tile_type, dst, src = l.strip().split('.')
+            if tile_type not in pipdata:
+                pipdata[tile_type] = []
+                tile_ports[tile_type] = set()
+
+            pipdata[tile_type].append((src, dst))
+            tile_ports[tile_type].add(src)
+            tile_ports[tile_type].add(dst)
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    tiledata = {}
+    pipdata = {}
+    ignpip = set()
+    tile_ports = {}
+
+    read_pip_data('pcie_int_interface_l.txt', pipdata, tile_ports)
+    read_pip_data('pcie_int_interface_r.txt', pipdata, tile_ports)
+
+    print("Loading tags from design.txt.")
+    with open("design.txt", "r") as f:
+        for line in f:
+            tile, pip, src, dst, pnum, pdir = line.split()
+
+            if not tile.startswith('PCIE_INT_INTERFACE'):
+                continue
+
+            pip_prefix, _ = pip.split(".")
+            tile_from_pip, tile_type = pip_prefix.split('/')
+            assert tile == tile_from_pip
+            _, src = src.split("/")
+            _, dst = dst.split("/")
+            pnum = int(pnum)
+            pdir = int(pdir)
+
+            if tile not in tiledata:
+                tiledata[tile] = {
+                    "type": tile_type,
+                    "pips": set(),
+                    "srcs": set(),
+                    "dsts": set()
+                }
+
+            tiledata[tile]["pips"].add((src, dst))
+            tiledata[tile]["srcs"].add(src)
+            tiledata[tile]["dsts"].add(dst)
+
+            if pdir == 0:
+                tiledata[tile]["srcs"].add(dst)
+                tiledata[tile]["dsts"].add(src)
+
+    for tile, pips_srcs_dsts in tiledata.items():
+        tile_type = pips_srcs_dsts["type"]
+        pips = pips_srcs_dsts["pips"]
+
+        for src, dst in pipdata[tile_type]:
+            if (src, dst) in ignpip:
+                pass
+            elif (src, dst) in pips:
+                segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
+            else:
+                segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/fuzzers/062-pcie-int-pips/generate.tcl b/fuzzers/062-pcie-int-pips/generate.tcl
new file mode 100644
index 00000000..aebb62c3
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/generate.tcl
@@ -0,0 +1,64 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc route_delay {} {
+    set nets [get_nets]
+
+    foreach net $nets {
+        set wire [get_wires -of_objects $net -filter { TILE_NAME =~ "*PCIE_INT_INTERFACE*" && NAME =~ "*IMUX*OUT*" }]
+
+        if { $wire == "" } {
+            continue
+        }
+
+        if { rand() < 0.30 } {
+            continue
+        }
+
+        set parts [split $wire "/"]
+        set tile_name [lindex $parts 0]
+        set wire_name [lindex $parts 1]
+
+        set delay_wire_name [string map {OUT DELAY} $wire_name]
+        set delay_node [get_nodes $tile_name/$delay_wire_name]
+
+        if { $delay_node == "" } {
+            exit 1
+        }
+
+        route_design -unroute -nets $net
+        puts "Attempting to route net $net through $delay_node."
+        route_via $net [list $delay_node]
+    }
+}
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
+
+    place_design -directive Quick
+    route_design -directive Quick
+
+    route_delay
+
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+    write_pip_txtdata design.txt
+}
+
+run
diff --git a/fuzzers/062-pcie-int-pips/pcie_int_interface_pip_list.tcl b/fuzzers/062-pcie-int-pips/pcie_int_interface_pip_list.tcl
new file mode 100644
index 00000000..9bf6d42b
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/pcie_int_interface_pip_list.tcl
@@ -0,0 +1,48 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+proc print_tile_pips {tile_type filename} {
+    set fp [open $filename w]
+    set pips [dict create]
+    foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] {
+        foreach pip [lsort [get_pips -of_objects  $tile]] {
+            set src [get_wires -uphill -of_objects $pip]
+            set dst [get_wires -downhill -of_objects $pip]
+
+            # Skip pips with disconnected nodes
+            set src_node [get_nodes -of_objects $src]
+
+            if { $src_node == {} } {
+                continue
+            }
+
+            set dst_node [get_nodes -of_objects $dst]
+            if { $dst_node == {} } {
+                continue
+            }
+
+            set src_wire [regsub {.*/} $src ""]
+            set src_delay_match [regexp {DELAY} $src_wire]
+
+            if { $src_delay_match } {
+                set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
+                if ![dict exists $pips $pip_string] {
+                    puts $fp $pip_string
+                    dict set pips $pip_string 1
+                }
+            }
+        }
+    }
+    close $fp
+}
+
+create_project -force -part $::env(XRAY_PART) design design
+set_property design_mode PinPlanning [current_fileset]
+open_io_design -name io_1
+
+print_tile_pips PCIE_INT_INTERFACE_L pcie_int_interface_l.txt
+print_tile_pips PCIE_INT_INTERFACE_R pcie_int_interface_r.txt
diff --git a/fuzzers/062-pcie-int-pips/ports.py b/fuzzers/062-pcie-int-pips/ports.py
new file mode 100644
index 00000000..eb9aea88
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/ports.py
@@ -0,0 +1,179 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+ports = {
+    "PCIE_2_1": [
+        ("CFGERRACSN", 1),
+        ("CFGERRATOMICEGRESSBLOCKEDN", 1),
+        ("CFGERRCORN", 1),
+        ("CFGERRCPLABORTN", 1),
+        ("CFGERRCPLTIMEOUTN", 1),
+        ("CFGERRCPLUNEXPECTN", 1),
+        ("CFGERRECRCN", 1),
+        ("CFGERRINTERNALCORN", 1),
+        ("CFGERRINTERNALUNCORN", 1),
+        ("CFGERRLOCKEDN", 1),
+        ("CFGERRMALFORMEDN", 1),
+        ("CFGERRMCBLOCKEDN", 1),
+        ("CFGERRNORECOVERYN", 1),
+        ("CFGERRPOISONEDN", 1),
+        ("CFGERRPOSTEDN", 1),
+        ("CFGERRURN", 1),
+        ("CFGFORCECOMMONCLOCKOFF", 1),
+        ("CFGFORCEEXTENDEDSYNCON", 1),
+        ("CFGINTERRUPTASSERTN", 1),
+        ("CFGINTERRUPTN", 1),
+        ("CFGINTERRUPTSTATN", 1),
+        ("CFGMGMTRDENN", 1),
+        ("CFGMGMTWRENN", 1),
+        ("CFGMGMTWRREADONLYN", 1),
+        ("CFGMGMTWRRW1CASRWN", 1),
+        ("CFGPMFORCESTATEENN", 1),
+        ("CFGPMHALTASPML0SN", 1),
+        ("CFGPMHALTASPML1N", 1),
+        ("CFGPMSENDPMETON", 1),
+        ("CFGPMTURNOFFOKN", 1),
+        ("CFGPMWAKEN", 1),
+        ("CFGTRNPENDINGN", 1),
+        ("CMRSTN", 1),
+        ("CMSTICKYRSTN", 1),
+        ("DBGSUBMODE", 1),
+        ("DLRSTN", 1),
+        ("DRPCLK", 1),
+        ("DRPEN", 1),
+        ("DRPWE", 1),
+        ("FUNCLVLRSTN", 1),
+        ("LL2SENDASREQL1", 1),
+        ("LL2SENDENTERL1", 1),
+        ("LL2SENDENTERL23", 1),
+        ("LL2SENDPMACK", 1),
+        ("LL2SUSPENDNOW", 1),
+        ("LL2TLPRCV", 1),
+        ("PIPECLK", 1),
+        ("PIPERX0CHANISALIGNED", 1),
+        ("PIPERX0ELECIDLE", 1),
+        ("PIPERX0PHYSTATUS", 1),
+        ("PIPERX0VALID", 1),
+        ("PIPERX1CHANISALIGNED", 1),
+        ("PIPERX1ELECIDLE", 1),
+        ("PIPERX1PHYSTATUS", 1),
+        ("PIPERX1VALID", 1),
+        ("PIPERX2CHANISALIGNED", 1),
+        ("PIPERX2ELECIDLE", 1),
+        ("PIPERX2PHYSTATUS", 1),
+        ("PIPERX2VALID", 1),
+        ("PIPERX3CHANISALIGNED", 1),
+        ("PIPERX3ELECIDLE", 1),
+        ("PIPERX3PHYSTATUS", 1),
+        ("PIPERX3VALID", 1),
+        ("PIPERX4CHANISALIGNED", 1),
+        ("PIPERX4ELECIDLE", 1),
+        ("PIPERX4PHYSTATUS", 1),
+        ("PIPERX4VALID", 1),
+        ("PIPERX5CHANISALIGNED", 1),
+        ("PIPERX5ELECIDLE", 1),
+        ("PIPERX5PHYSTATUS", 1),
+        ("PIPERX5VALID", 1),
+        ("PIPERX6CHANISALIGNED", 1),
+        ("PIPERX6ELECIDLE", 1),
+        ("PIPERX6PHYSTATUS", 1),
+        ("PIPERX6VALID", 1),
+        ("PIPERX7CHANISALIGNED", 1),
+        ("PIPERX7ELECIDLE", 1),
+        ("PIPERX7PHYSTATUS", 1),
+        ("PIPERX7VALID", 1),
+        ("PLDIRECTEDLINKAUTON", 1),
+        ("PLDIRECTEDLINKSPEED", 1),
+        ("PLDIRECTEDLTSSMNEWVLD", 1),
+        ("PLDIRECTEDLTSSMSTALL", 1),
+        ("PLDOWNSTREAMDEEMPHSOURCE", 1),
+        ("PLRSTN", 1),
+        ("PLTRANSMITHOTRST", 1),
+        ("PLUPSTREAMPREFERDEEMPH", 1),
+        ("SYSRSTN", 1),
+        ("TL2ASPMSUSPENDCREDITCHECK", 1),
+        ("TL2PPMSUSPENDREQ", 1),
+        ("TLRSTN", 1),
+        ("TRNRDSTRDY", 1),
+        ("TRNRFCPRET", 1),
+        ("TRNRNPOK", 1),
+        ("TRNRNPREQ", 1),
+        ("TRNTCFGGNT", 1),
+        ("TRNTDLLPSRCRDY", 1),
+        ("TRNTECRCGEN", 1),
+        ("TRNTEOF", 1),
+        ("TRNTERRFWD", 1),
+        ("TRNTSOF", 1),
+        ("TRNTSRCDSC", 1),
+        ("TRNTSRCRDY", 1),
+        ("TRNTSTR", 1),
+        ("USERCLK2", 1),
+        ("USERCLK", 1),
+        ("CFGERRAERHEADERLOG", 128),
+        ("TRNTD", 128),
+        ("CFGDEVID", 16),
+        ("CFGSUBSYSID", 16),
+        ("CFGSUBSYSVENDID", 16),
+        ("CFGVENDID", 16),
+        ("DRPDI", 16),
+        ("PIPERX0DATA", 16),
+        ("PIPERX1DATA", 16),
+        ("PIPERX2DATA", 16),
+        ("PIPERX3DATA", 16),
+        ("PIPERX4DATA", 16),
+        ("PIPERX5DATA", 16),
+        ("PIPERX6DATA", 16),
+        ("PIPERX7DATA", 16),
+        ("CFGPMFORCESTATE", 2),
+        ("DBGMODE", 2),
+        ("PIPERX0CHARISK", 2),
+        ("PIPERX1CHARISK", 2),
+        ("PIPERX2CHARISK", 2),
+        ("PIPERX3CHARISK", 2),
+        ("PIPERX4CHARISK", 2),
+        ("PIPERX5CHARISK", 2),
+        ("PIPERX6CHARISK", 2),
+        ("PIPERX7CHARISK", 2),
+        ("PLDIRECTEDLINKCHANGE", 2),
+        ("PLDIRECTEDLINKWIDTH", 2),
+        ("TRNTREM", 2),
+        ("CFGDSFUNCTIONNUMBER", 3),
+        ("CFGFORCEMPS", 3),
+        ("PIPERX0STATUS", 3),
+        ("PIPERX1STATUS", 3),
+        ("PIPERX2STATUS", 3),
+        ("PIPERX3STATUS", 3),
+        ("PIPERX4STATUS", 3),
+        ("PIPERX5STATUS", 3),
+        ("PIPERX6STATUS", 3),
+        ("PIPERX7STATUS", 3),
+        ("PLDBGMODE", 3),
+        ("TRNFCSEL", 3),
+        ("CFGMGMTDI", 32),
+        ("TRNTDLLPDATA", 32),
+        ("CFGMGMTBYTEENN", 4),
+        ("CFGERRTLPCPLHEADER", 48),
+        ("CFGAERINTERRUPTMSGNUM", 5),
+        ("CFGDSDEVICENUMBER", 5),
+        ("CFGPCIECAPINTERRUPTMSGNUM", 5),
+        ("PL2DIRECTEDLSTATE", 5),
+        ("PLDIRECTEDLTSSMNEW", 6),
+        ("CFGDSN", 64),
+        ("MIMRXRDATA", 68),
+        ("MIMTXRDATA", 69),
+        ("CFGDSBUSNUMBER", 8),
+        ("CFGINTERRUPTDI", 8),
+        ("CFGPORTNUMBER", 8),
+        ("CFGREVID", 8),
+        ("DRPADDR", 9),
+        ("CFGMGMTDWADDR", 10),
+    ]
+}
diff --git a/fuzzers/062-pcie-int-pips/top.py b/fuzzers/062-pcie-int-pips/top.py
new file mode 100644
index 00000000..36c26ce3
--- /dev/null
+++ b/fuzzers/062-pcie-int-pips/top.py
@@ -0,0 +1,86 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import random
+import math
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.lut_maker import LutMaker
+from prjxray.db import Database
+
+from ports import ports
+
+
+def print_site(ports, luts, site, site_type):
+    verilog_ports = ""
+    verilog_wires = ""
+
+    for port, width in ports:
+        verilog_ports += """
+    .{port}({port}_{site}),""".format(
+            port=port, site=site)
+        verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site)
+
+        for idx in range(0, width):
+            verilog_wires += "assign {}_{}[{}] = {};\n".format(
+                port, site, idx, luts.get_next_output_net())
+
+        verilog_wires += "\n"
+
+    verilog_ports = verilog_ports.rstrip(",")
+
+    print(
+        """
+{wires}
+
+(* KEEP, DONT_TOUCH, LOC = "{site}" *)
+{site_type} {site}_instance (
+{ports}
+);""".format(
+            wires=verilog_wires,
+            ports=verilog_ports,
+            site=site,
+            site_type=site_type))
+
+
+def main():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+
+    luts = LutMaker()
+
+    def gen_sites(desired_site_type):
+        for tile_name in sorted(grid.tiles()):
+            loc = grid.loc_of_tilename(tile_name)
+            gridinfo = grid.gridinfo_at_loc(loc)
+            for site, site_type in gridinfo.sites.items():
+                if site_type == desired_site_type:
+                    yield tile_name, site
+
+    print('''
+module top();
+
+    (* KEEP, DONT_TOUCH *)
+    LUT6 dummy();
+''')
+
+    for site_type in ["PCIE_2_1"]:
+        for _, site in gen_sites(site_type):
+            print_site(ports[site_type], luts, site, site_type)
+
+    for l in luts.create_wires_and_luts():
+        print(l)
+
+    print('endmodule')
+
+
+if __name__ == "__main__":
+    main()
diff --git a/utils/mergedb.sh b/utils/mergedb.sh
index c3eaef57..98383d4e 100755
--- a/utils/mergedb.sh
+++ b/utils/mergedb.sh
@@ -160,6 +160,12 @@ case "$1" in
 	pcie_bot)
 		cp "$2" "$tmp1" ;;
 
+	pcie_int_interface_l)
+		sed < "$2" > "$tmp1" -e 's/^PCIE_INT_INTERFACE\./PCIE_INT_INTERFACE_L./' ;;
+
+	pcie_int_interface_r)
+		sed < "$2" > "$tmp1" -e 's/^PCIE_INT_INTERFACE\./PCIE_INT_INTERFACE_R./' ;;
+
 	gtp_common)
 		cp "$2" "$tmp1" ;;