From 703688478492bba3b621fc9f680a5f6da4c1d283 Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Fri, 15 Jan 2021 13:11:20 +0100
Subject: [PATCH] 063-gtp-common: add inverted and in_use features

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 fuzzers/063-gtp-common-conf/generate.py | 18 +++++--
 fuzzers/063-gtp-common-conf/top.py      | 66 +++++++++++++++++--------
 2 files changed, 60 insertions(+), 24 deletions(-)

diff --git a/fuzzers/063-gtp-common-conf/generate.py b/fuzzers/063-gtp-common-conf/generate.py
index dda8cf81..efe3d5ca 100644
--- a/fuzzers/063-gtp-common-conf/generate.py
+++ b/fuzzers/063-gtp-common-conf/generate.py
@@ -36,11 +36,15 @@ def main():
         attrs = json.load(attr_file)
 
     print("Loading tags")
-    with open('params.json') as f:
+    with open("params.json") as f:
         params = json.load(f)
 
-        site = params['site']
+    site = params["site"]
+    in_use = params["IN_USE"]
 
+    segmk.add_site_tag(site, "IN_USE", in_use)
+
+    if in_use:
         for param, param_info in attrs.items():
             value = params[param]
             param_type = param_info["type"]
@@ -65,7 +69,15 @@ def main():
                 ]
 
                 for i in range(param_digits):
-                    segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
+                    segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
+
+        for param, invert in [("GTGREFCLK1", 0), ("GTGREFCLK0", 0),
+                              ("PLL0LOCKDETCLK", 1), ("PLL1LOCKDETCLK",
+                                                      1), ("DRPCLK", 1)]:
+            if invert:
+                segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
+            else:
+                segmk.add_site_tag(site, "INV_" + param, params[param])
 
     segmk.compile(bitfilter=bitfilter)
     segmk.write()
diff --git a/fuzzers/063-gtp-common-conf/top.py b/fuzzers/063-gtp-common-conf/top.py
index cdad5b9b..f4b6dda2 100644
--- a/fuzzers/063-gtp-common-conf/top.py
+++ b/fuzzers/063-gtp-common-conf/top.py
@@ -45,8 +45,14 @@ def gen_sites():
 
 
 def main():
-    print('''
-module top();
+    print(
+        '''
+module top(
+    input wire in,
+    output wire out
+);
+
+assign out = in;
 ''')
 
     site_name, site_type = gen_sites()
@@ -63,30 +69,48 @@ module top();
     with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
         attrs = json.load(attrs_file)
 
-    for param, param_info in attrs.items():
-        param_type = param_info["type"]
-        param_values = param_info["values"]
-        param_digits = param_info["digits"]
+    in_use = bool(random.randint(0, 9))
+    params["IN_USE"] = in_use
 
-        if param_type == INT:
-            value = random.choice(param_values)
-            value_str = value
-        else:
-            assert param_type == BIN
-            value = random.randint(0, param_values[0])
-            value_str = "{digits}'b{value:0{digits}b}".format(
-                value=value, digits=param_digits)
+    if in_use:
+        for param, param_info in attrs.items():
+            param_type = param_info["type"]
+            param_values = param_info["values"]
+            param_digits = param_info["digits"]
 
-        params[param] = value
+            if param_type == INT:
+                value = random.choice(param_values)
+                value_str = value
+            else:
+                assert param_type == BIN
+                value = random.randint(0, param_values[0])
+                value_str = "{digits}'b{value:0{digits}b}".format(
+                    value=value, digits=param_digits)
 
-        verilog_attr += """
-    .{}({}),""".format(param, value_str)
+            params[param] = value
 
-    verilog_attr = verilog_attr.rstrip(",")
-    verilog_attr += "\n)"
+            verilog_attr += """
+        .{}({}),""".format(param, value_str)
+
+        for param in ["GTGREFCLK1", "GTGREFCLK0", "PLL0LOCKDETCLK",
+                      "PLL1LOCKDETCLK", "DRPCLK"]:
+            is_inverted = random.randint(0, 1)
+
+            params[param] = is_inverted
+
+            verilog_attr += """
+        .IS_{}_INVERTED({}),""".format(param, is_inverted)
+
+        verilog_attr = verilog_attr.rstrip(",")
+        verilog_attr += "\n)"
+
+        print("(* KEEP, DONT_TOUCH *)")
+        print(
+            """GTPE2_COMMON {} gtp_common (
+    .GTREFCLK0(1'b0),
+    .GTREFCLK1(1'b0)
+);""".format(verilog_attr))
 
-    print("(* KEEP, DONT_TOUCH *)")
-    print("GTPE2_COMMON {} gtp_common ();".format(verilog_attr))
     print("endmodule")
 
     with open('params.json', 'w') as f: